>
> On Thu, 15 Feb 2001, Kanoj Sarcar wrote:
>
> > No. All architectures do not have this problem. For example, if the
> > Linux "dirty" (not the pte dirty) bit is managed by software, a fault
> > will actually be taken when processor 2 tries to do the write. The fault
> > is solely to make sure that the Linux "dirty" bit can be tracked. As long
> > as the fault handler grabs the right locks before updating the Linux "dirty"
> > bit, things should be okay. This is the case with mips, for example.
> >
> > The problem with x86 is that we depend on automatic x86 dirty bit
> > update to manage the Linux "dirty" bit (they are the same!). So appropriate
> > locks are not grabbed.
>
> Will you please go off and prove that this "problem" exists on some x86
> processor before continuing this rant? None of the PII, PIII, Athlon,
And will you please stop behaving like this is not an issue?
> K6-2 or 486s I checked exhibited the worrisome behaviour you're
And I maintain that this kind of race condition can not be tickled
deterministically. There might be some piece of logic (or absence of it),
that can show that your finding of a thousand runs is not relevant.
> speculating about, plus it is logically consistent with the statements the
> manual does make about updating ptes; otherwise how could an smp os
Don't say this anymore, specially if you can not point me to the specs.
> perform a reliable shootdown by doing an atomic bit clear on the present
> bit of a pte?
OS clears present bit, processors can keep using their TLBs and access
the page, no problems at all. That is why after clearing the present bit,
the processor must flush all tlbs before it can assume no one is using
the page. Hardware updated access bit could also be a problem, but an
error there does not destroy data, it just leads the os to choosing the
wrong page to evict during memory pressure.
Kanoj
>
> -ben
>
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This archive was generated by hypermail 2b29 : Thu Feb 15 2001 - 21:00:27 EST