On Fri, 22 Feb 2002 19:20:24 +0100
Adam Lackorzynski <adam@os.inf.tu-dresden.de> wrote:
> On Fri Feb 22, 2002 at 18:04:29 +0100, Stephan von Krawczynski wrote:
> > Your config is not identical to the one I sent. If you want to find
> > out what the problem is, you must first try to produce a setup that is
> > known good. So simply use my config, even if it contains stuff you
> > don't need, and especially if it does not contain stuff you want.
> > Your primary goal is: let the box boot.
>
> Yours (+serial console) doesn't work either, so I stripped out most
> unneeded things. I'm going to rip out all cards except net and graphics
> to see if that helps but that has to wait till Monday...
>
> BTW: I just got this:
> Using local APIC timer interrupts.
> calibrating APIC timer ...
> .... CPU clock speed is 937.5536 MHz.
> ..... host bus clock speed is 133.9358 MHz.
> cpu: 0, clocks: 1339358, slice: 446452
> CPU0<T0:1339344,T1:892880,D:12,S:446452,C:1339358>
> cpu: 1, clocks: 1339358, slice: 446452
> CPU1<T0:1339344,T1:446432,D:8,S:446452,C:1339358>
> checking TSC synchronization across CPUs:
> BIOS BUG: CPU#0 improperly initialized, has -6 usecs TSC skew! FIXED.
> BIOS BUG: CPU#1 improperly initialized, has 6 usecs TSC skew! FIXED.
> Waiting on wait_init_idle (map = 0x
>
>
> Maybe this means something...
Aha, here is my output on 2 x 1 GHz:
<4>Using local APIC timer interrupts.
<4>calibrating APIC timer ...
<4>..... CPU clock speed is 1004.5421 MHz.
<4>..... host bus clock speed is 133.9388 MHz.
<4>cpu: 0, clocks: 1339388, slice: 446462
<4>CPU0<T0:1339376,T1:892912,D:2,S:446462,C:1339388>
<4>cpu: 1, clocks: 1339388, slice: 446462
<4>CPU1<T0:1339376,T1:446448,D:4,S:446462,C:1339388>
<4>checking TSC synchronization across CPUs: passed.
<4>Waiting on wait_init_idle (map = 0x2)
<4>All processors have done init_idle
And the same part for 2 x 933 MHz:
<4>Using local APIC timer interrupts.
<4>calibrating APIC timer ...
<4>..... CPU clock speed is 937.5672 MHz.
<4>..... host bus clock speed is 133.9380 MHz.
<4>cpu: 0, clocks: 1339380, slice: 446460
<4>CPU0<T0:1339376,T1:892912,D:4,S:446460,C:1339380>
<4>cpu: 1, clocks: 1339380, slice: 446460
<4>CPU1<T0:1339376,T1:446448,D:8,S:446460,C:1339380>
<4>checking TSC synchronization across CPUs: passed.
<4>Waiting on wait_init_idle (map = 0x2)
<4>All processors have done init_idle
I would say this means the TSC skew fix is broken and shooting down your box. What do you think, Alan?
Regards,
Stephan
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This archive was generated by hypermail 2b29 : Sat Feb 23 2002 - 21:00:50 EST