>> Was there some reason you really need this on P4s? I seem to recall something
>> to do with timer interrupts, but don't remember exactly.
>
> Without the explicit balancing, _every_single_ external interrupt comes in
> on CPU0 on a P4.
>
> The P4 local APIC doesn't do irq scheduling in hardware (never mind that
> Intel documented it as architecture behaviour in earlier local APICs)
I know, but you pays your money, you choose your breakage ;-)
I can't help feeling that the real solution is to program the TPR like Intel intended,
instead of frigging with the IO-APIC, especially when the the code that does the
frigging is written with incorrect assumuptions.
Forcing it on for every machine just because P4s are borked sounds wrong.
The current code has several issues (including, I believe, being frequency
dependent on jiffies ... bad with 1000 HZ), so we really do need to disable
it for many machines. Getting rid of the negative config option is easy though.
M.
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This archive was generated by hypermail 2b29 : Thu Aug 15 2002 - 22:00:33 EST