L1_CACHE_SHIFT value for P4 ?

From: Margit Schubert-While (margit@margit.com)
Date: Thu Nov 21 2002 - 09:39:33 EST


Just for the record - my x86info

Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries.
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
L1 Data cache:
         Size: 8KB Sectored, 4-way associative.
         line size=64 bytes.
No L3 cache
Instruction trace cache:
         Size: 12K uOps 8-way associative.
L2 unified cache:
         Size: 512KB Sectored, 8-way associative.
         line size=64 bytes.

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