Re: Page fault scalability patch V18: Drop first acquisition of ptl

[Benjamin Herrenschmidt]

> However, if this pte_cmpxchg() thing is used for removing access, then
> sparc64 can't use it.  In such a case a race in the TLB handler would
> result in using an invalid PTE.  I could "spin" on some lock bit, but
> there is no way I'm adding instructions to the carefully constructed
> TLB miss handler assembler on sparc64 just for that :-)

Can't you add a lock bit in the PTE itself like we do on ppc64 hash
refill ?

Ok, ok, you don't want to add instructions, fair enough :) On ppc64, I
had to do that to close some nasty race we had in the hash refill, but
it came almost for free as we already had an atomic loop in there.

Ben.


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