Re: Page fault scalability patch V18: Drop first acquisition of ptl

[Nick Piggin]

Benjamin Herrenschmidt wrote:

> > However, if this pte_cmpxchg() thing is used for removing access, then
> > sparc64 can't use it.  In such a case a race in the TLB handler would
> > result in using an invalid PTE.  I could "spin" on some lock bit, but
> > there is no way I'm adding instructions to the carefully constructed
> > TLB miss handler assembler on sparc64 just for that :-)
>
> Can't you add a lock bit in the PTE itself like we do on ppc64 hash
> refill ?

You don't want to do that for all architectures, as I said earlier.
eg. i386 can concurrently set the dirty bit with the MMU (which won't
honour the lock).

So you then need an atomic lock, atomic pte operations, and atomic
unlock where previously you had only the atomic pte operation. This is
disastrous for performance.


-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/