Re: increased translation cache footprint in v2.6

[David S. Miller]

From: Marcelo Tosatti <marcelo.tosatti@xxxxxxxxxxxx>
Date: Sun, 26 Jun 2005 15:52:10 -0300

> Well, a TLB entry might cache different sized pages. The platform
> support 4kb, 16kb and 8Mb (IIRC, maybe some other size also).  The
> bigger pages (8Mb) are only used to map 8Mbytes of instruction at
> KERNELBASE, 24Mbytes of data (3 8Mbyte entries) also at KERNELBASE
> and another 8Mbytes of the configuration registers memory space,
> which lives outside RAM space.

Why don't you use 8MB TLB entries when there is a miss to
one of the PAGE_OFFSET pages?  I'm not saying to lock them,
just to use large 8MB TLB entries when a miss is taken for
kernel data accesses to where the kernel maps all of lowmem.
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