Re: question on memory barrier

[Jesse Barnes]

On Wednesday, August 24, 2005 12:48 pm, Andy Isaacson wrote:
> The first register write will be completed before the second register
> write because you use writel, which is defined to have the semantics
> you want.  (It uses a platform-specific method to guarantee this,
> possibly "volatile" or "asm("eieio")" or whatever method your platform
> requires.)

writel() ensures ordering?  Only from one CPU, another CPU issuing a 
write at some later time may have its write arrive first.  See 
Documentation/io_ordering.txt for some documentation I put together on 
this issue.

Jesse
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