Re: AMD64, 4GB, mttr questions

[Robert Hancock]

Prakash Punnoor wrote:
> I have a machine with 4GB RAM, an Athlon64 X2 and following mttr entries:
>
> reg00: base=0x00000000 (   0MB), size=4096MB: write-back, count=1
> reg01: base=0x100000000 (4096MB), size=2048MB: write-back, count=1
> reg02: base=0x80000000 (2048MB), size=2048MB: uncachable, count=1
>
> First of all, why is there an uncachable region? Is it the upper half of 
> memory? Or is this just a hole and the remaining 2GB are seated at 
> 0x100000000 ?

Your e820 memory map shows the first 2GB of RAM is at 0-2GB and the 
remaining 2GB is at 4-6GB, so yes there is a hole. This doesn't explain 
why all of 0-4GB is set as write-back and then the top half of it is 
also set as uncacheable. This will presumably have been set up by the 
BIOS though, I don't think the kernel does this.	

> I am also wondering why the kernel doesn't propery set up write-combining 
> regions: (I noticed this on 32bit x86, as well, on various machines)

Just because there is MMIO there, does not mean it can be safely set as 
write combining. For devices that support write combining, I believe 
it's the responsibility of the driver (or in the case of a graphics 
card, X) to set this up if it wants. Generally this is only done for 
graphics cards due to the limited number of MTRR entries.

> X also comlains about this:
>
> mtrr: type mismatch for b0000000,2000000 old: write-back new: write-combining

Sounds like X is doing something reasonable, that range shouldn't have 
been set as write-back in the first place. Presumably the fault of the 
BIOS however.

--
Robert Hancock      Saskatoon, SK, Canada
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Home Page: http://www.roberthancock.com/

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