Re: [PATCH] [21/58] i386: Reserve the right performance counter for the Intel PerfMon NMI watchdog

[Andi Kleen]

On Thursday 19 July 2007 12:21:45 BjÃrn Steinbrink wrote:
> On 2007.07.19 11:55:06 +0200, Andi Kleen wrote:
> > 
> > From: [** iso-8859-1 charset **] BjörnSteinbrink <B.Steinbrink@xxxxxx>
> > 
> > The Intel PerfMon NMI watchdog was using the generic reservation
> > function which always reserves the first performance counter. But the
> > watchdog actually uses the second performance counter, thus we need a
> > specialised function.
> 
> Ah, almost forgot about that patch. Actually, thanks to your fix that
> basically reverted the msr->offset conversation to its 2.6.21
> implementation, single_msr_reserve has sane semantics now and does just
> what the name suggests (before, the wd_ops entries had to store the
> "base" msrs, so it was really a first_msr_reserve).
> 
> With wd_ops->perfctr no longer needed to be the base msr, we can just
> fix that value for the arch perfmon watchdog. (And maybe we should
> remove the values for those implementations that don't employ the
> single_msr_reserve() stuff?)

I replaced the patch with the new patch, thanks

-Andi

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