Re: [PATCH -tip] perf_counter/x86: Correct some event and umaskvalues for Intel processors

[Ingo Molnar]

* Yong Wang <yong.y.wang@xxxxxxxxxxxxxxx> wrote:

> > > Btw, one thing I don't quite understand is why you aliased 
> > > dtlb-write-ops to l1d-write-ops when setting event and umask 
> > > values. Are they the same event?
> > 
> > No, they are indeed different events - that's a bug in the table, 
> > good spotting. Mind sending a (tested) patch for it?
> > 
> 
> I'm a little confused. By dtlb-write-ops, do you want to count the 
> number of times that DTLB is accessed due to store operations or 
> the number of times that DTLB entries are written to, i.e. 
> updated?

ah - i think what makes most sense is the (micro-)instruction 
direction: i.e. TLB entry accessed due to store operations.

Also, are TLB entries updated typically after they get established? 
Things like the dirty or accessed bit in the PTE are written out to 
caches immediately, so that bit probably does not linger in the PTE.

> Btw, do you know whether virtual cache is employed or not on 
> atom/core2/nehalem so that tlb won't be accessed when accessing l1 
> caches?

Hm, last i checked the L2 was all physically indexed. The short 
experiment with (partial?) virtual indexing in P4 was a ... 
spectacular failure IMO.

This doesnt mean the counters wont under-count. The TLB hotpath is 
probably one of the most important critical paths in a CPU, so it's 
fair for a CPU not to count those accesses in the PMU, to squeeze 
out a few more gates. (I havent validated the TLB counters on 
core2/nehalem to that level yet so i dont know for sure how this is 
laid out in practice.)

	Ingo
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