Re: [PATCH 4/7] perf, x86: Implement IBS interrupt handler

[Ingo Molnar]

* Don Zickus <dzickus@xxxxxxxxxx> wrote:

> On Mon, Aug 01, 2011 at 05:21:43PM +0200, Peter Zijlstra wrote:
> > On Mon, 2011-08-01 at 07:32 +0200, Robert Richter wrote:
> > > > So IBS cannot trigger the whole unknown NMI business? Wouldn't ibs_op
> > > > triggering while ibs_fetch just started latch the NMI line, the
> > > > in-progress NMI would handle both, and we then end up with a spare NMI?
> > > 
> > > Ok, I will run some excessive testing of this. If this turns out to be
> > > a problem I will change the code. Could this be on top of this patch
> > > set then? 
> > 
> > Sure, if you somehow end up duplicating some logic I think you 
> > know about this common.c file you proposed ;-)
> > 
> > I kinda lost the current state of affairs wrt spurious NMIs, I 
> > think there's still a few reports out there. I recently read 
> > through some Intel errata and found the Intel PMU can send double 
> > PMIs under some circumstances (just to keep life interesting).
> 
> I tried looking into but everytime I applied workarounds for Intel 
> errata I wound up with more unknown NMIs and proving that a couple 
> of them worked (with trace_printks) seemed elusive.  I got 
> frustrated and left it alone.
> 
> But yeah, Intel's perf has so many errata that I think if you kick 
> the box while running perf you can generate an unknown NMI.

Hence the only sane approach is to just tolerate spurious NMIs and 
only annoy the user with them if there's *way* too many of them or 
so.

Thanks,

	Ingo
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