Re: [PATCH 4/5] perf, x86: Support full width counting v3

[Ingo Molnar]

* Andi Kleen <andi@xxxxxxxxxxxxxx> wrote:

> From: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> 
> Recent Intel CPUs like Haswell and IvyBridge have a new 
> alternative MSR range for perfctrs that allows writing the 
> full counter width. Enable this range if the hardware reports 
> it using a new capability bit.
> 
> This lowers the overhead of perf stat slightly because it has 
> to do less interrupts to accumulate the counter value. On 
> Haswell it also avoids some problems with TSX aborting when 
> the end of the counter range is reached.

The changelog does not adequately explain why this patch is 
critical for basic Haswell enablement. "Avoids some problems 
with TSX aborting" is not very helpful.

Thanks,

	Ingo
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