Re: [PATCH 4/5] perf, x86: Support full width counting v3

[Andi Kleen]

On Fri, Feb 22, 2013 at 02:46:30PM +0100, Ingo Molnar wrote:
> 
> * Andi Kleen <andi@xxxxxxxxxxxxxx> wrote:
> 
> > From: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> > 
> > Recent Intel CPUs like Haswell and IvyBridge have a new 
> > alternative MSR range for perfctrs that allows writing the 
> > full counter width. Enable this range if the hardware reports 
> > it using a new capability bit.
> > 
> > This lowers the overhead of perf stat slightly because it has 
> > to do less interrupts to accumulate the counter value. On 
> > Haswell it also avoids some problems with TSX aborting when 
> > the end of the counter range is reached.
> 
> The changelog does not adequately explain why this patch is 
> critical for basic Haswell enablement. "Avoids some problems 
> with TSX aborting" is not very helpful.

Updated description below. I don't want you from stop reviewing
the rest of the patches, so I'm not posting a new series
for now just for a new description. Please keep reading.
You may make it through to the end.

---

Recent Intel CPUs like Haswell and IvyBridge have a new
alternative MSR range for perfctrs that allows writing the
full counter width. Enable this range if the hardware reports
it using a new capability bit.

This lowers the overhead of perf stat slightly because it has
to do less interrupts to accumulate the counter value. On
Haswell it also avoids some problems with TSX aborting when
the end of the counter range is reached. This can be observed
when the checkpoint flag has been set, which has been enabled
by the basic PMU patch. An overflow will abort the transaction
and set the counter back. If the counter is near the overflow
before the transaction this could happen continuously, forcing
a transaction to continuously abort.
This is a partial fix, but it makes the overflows much less 
likely by using a larger counter, to lower the probability of the
event. Additional counter measures are in the additional extended
Haswell patchkit.

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