Re: [PATCH] perf, x86: add Intel IvyBridge event schedulingconstraints

[yqzhang]

Hi Stephane,

I was wondering what the differences are between
CYCLE_ACTIVITY.CYCLES_**_PENDING and CYCLE_ACTIVITY.STALLS_**_PENDING,
because I could only find following events in the SDM, which seem to be
different from the ones provided here. Correct me if I'm wrong.

A3H 01H CYCLE_ACTIVITY.CYCLES_L2_PENDING
  - Cycles with pending L2 miss loads. Set Cmask=2 tocount cycle. Use only
when HTT is off
A3H 02H CYCLE_ACTIVITY.CYCLES_LDM_PENDING
  - Cycles with pending memory loads. Set Cmask=2 to count cycle.
A3H 05H CYCLE_ACTIVITY.STALLS_L2_PENDING
  - Number of loads missed L2. Use only when HTT is off
A3H 08H CYCLE_ACTIVITY.CYCLES_L1D_PENDING
  - Cycles with pending L1 cache miss loads. SetCmask=8 to count cycle.PMC2
only

Thanks a lot!



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