[PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Punnaiah Choudary Kalluri]

Add bindings documentation for Zynq Quad SPI driver.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xxxxxxxxxx>
---
 .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   26 ++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
new file mode 100644
index 0000000..88e00f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
@@ -0,0 +1,26 @@
+Xilinx Zynq QSPI controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible		: Should be "xlnx,zynq-qspi-1.0".
+- reg			: Physical base address and size of QSPI registers map.
+- interrupts		: Property with a value describing the interrupt
+			  number.
+- interrupt-parent	: Must be core interrupt controller
+- clock-names		: List of input clock names - "ref_clk", "aper_clk"
+			  (See clock bindings for details).
+- clocks		: Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs		: Number of chip selects used.
+
+Example:
+	qspi@e000d000 {
+		compatible = "xlnx,zynq-qspi-1.0";
+		clock-names = "ref_clk", "aper_clk";
+		clocks = <&clkc 10>, <&clkc 43>;
+		interrupt-parent = <&ps7_scugic_0>;
+		interrupts = <0 19 4>;
+		num-cs = /bits/ 16 <1>;
+		reg = <0xe000d000 0x1000>;
+	};
-- 
1.7.9.5


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