Re: [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold

[Peter Zijlstra]

On Wed, May 28, 2014 at 09:51:44AM -0700, Andi Kleen wrote:
> > The only part I don't quite follow here is this:
> >                       if (__test_and_set_bit(bit, (unsigned long *)&status))
> >                                 continue;
> > 
> > Which seems to indicate the code is making sure each counter is
> > processed only once. But it can only be processed once, if you have
> > only one record. And if you have multiple, you want to be able to
> > handle the same counter multiple times, at least once perf PEBS
> > record. So I am a bit confused about this test.
> 
> Each PEBS record is only for a single counter overflow. So it
> always should only be a single perf event.

OK, so what Stephane said, that two counter's having their assist on the
exact same cycle results in but a single record is false? That would be
good.

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