Re: [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold

[Peter Zijlstra]

On Wed, May 28, 2014 at 10:45:45AM -0700, Andi Kleen wrote:
> > So the window is fairly large for another to slip in, esp if you have a
> > fast (say inst-ret) and a slow (say br-misp) event.
> 
> yes, but unless you have really small periods it's still very unlikely
> that they synchronize, so it will only happen very rarely.  And the
> rare cases won't affect the statistics very much.

Sure, but it might be an information leak... Not sure how severe these
are, but again.. it blows to have to worry about this when it would've
been 'trivial' to actually fix.

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