Re: [PATCH 1/2] ARM: LPAE: load upper bits of early TTBR0/TTBR1

[Konstantin Khlebnikov]

On 2014-08-28 15:03, Will Deacon wrote:
> On Wed, Aug 27, 2014 at 04:45:24PM +0100, Jassi Brar wrote:
> > On Wed, Aug 27, 2014 at 9:01 PM, Konstantin Khlebnikov <koct9i@xxxxxxxxx> wrote:
> > > On Wed, Aug 27, 2014 at 7:26 PM, Jassi Brar <jassisinghbrar@xxxxxxxxx> wrote:
> > > > It seems the patch wasn't tested on any real platform, I did on my
> > > > CA15 based platform - it breaks boot. Simply reverting the patch gets
> > > > it going again. I am happy to try any fix.
> > > Please try to remove adcls line.
> > > Seems like this affects only systems where PHYS_OFFSET == PAGE_OFFSET.
> > >
> > > --- a/arch/arm/mm/proc-v7-3level.S
> > > +++ b/arch/arm/mm/proc-v7-3level.S
> > > @@ -146,7 +146,6 @@ ENDPROC(cpu_v7_set_pte_ext)
> > >          mov     \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
> > >          mov     \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT             @ lower bits
> > >          addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
> > > -       adcls   \tmp, \tmp, #0
> > >          mcrr    p15, 1, \ttbr1, \tmp, c2                        @ load TTBR1
> > >          mov     \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
> > >          mov     \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT             @ lower bits
> > Yup, restores boot.
> Can somebody write this up as a proper patch and put it in the patch system
> please?

Ok. Done.

http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8132/1

> Will

ARM: LPAE: drop wrong carry flag correction after adding TTBR1_OFFSET

From: Konstantin Khlebnikov <k.khlebnikov@xxxxxxxxxxx>

In commit 7fb00c2fca4b6c58be521eb3676cf4b4ba8dde3b ("ARM: 8114/1: LPAE:
load upper bits of early TTBR0/TTBR1") part which fixes carrying in adding
TTBR1_OFFSET to TTRR1 was wrong:

	addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
	adcls   \tmp, \tmp, #0

addls doesn't update flags, adcls adds carry from cmp above:

	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET?

Condition 'ls' means carry flag is clear or zero flag is set, thus only one
case is affected: when PHYS_OFFSET == PAGE_OFFSET.

It seems safer to remove this fixup. Bug is here for ages and nobody
complained. Let's fix it separately.

Signed-off-by: Konstantin Khlebnikov <k.khlebnikov@xxxxxxxxxxx>
Reported-and-tested-by: Jassi Brar <jassisinghbrar@xxxxxxxxx>
---
 arch/arm/mm/proc-v7-3level.S |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 1a24e92..b64e67c 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -146,7 +146,6 @@ ENDPROC(cpu_v7_set_pte_ext)
 	mov	\tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
 	mov	\ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT		@ lower bits
 	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
-	adcls	\tmp, \tmp, #0
 	mcrr	p15, 1, \ttbr1, \tmp, c2			@ load TTBR1
 	mov	\tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
 	mov	\ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT		@ lower bits