Re: [PATCH v2 2/3] MIPS: Setup an instruction emulation in VDSO protected page instead of user stack
From: James Hogan
Date: Thu Oct 09 2014 - 19:40:57 EST
On Thu, Oct 09, 2014 at 04:10:15PM -0700, Leonid Yegoshin wrote:
> >> Small stack of emulation blocks is supported because nested traps are possible
> >> in MIPS32/64 R6 emulation mix with FPU emulation.
> > Could you please clarify how this nesting of emulation blocks could
> > happen now that signals are handled more cleanly.
> > I.e. isn't the emuframe stuff only required for instructions in branch
> > delay slots, and branches shouldn't be in branch delay slots anyway, so
> > I don't get how they could nest.
> It may be a case for mix of FPU and MIPS R6 emulations. I just keep both
> emulators separate as much as possible but I assume that without prove
> it may be stackable - some rollback is needed to join both and it may
> (probably) cause a double emulation setup - dsemul may be called twice
> for the same pair of instructions. I didn't see that yet, honestly and
> you may be right.
If the only time they're used is for emulation of a branch delay slot
instruction which should never be another branch, and signals always
undo the emuframe before being handled (btw, should the BD bit in cause
get set if rewinding for signal handlers/gdb?), then it stands to reason
it should never nest.
You could then avoid the whole stack and per-thread thing and just have
a maximum of one emuframe dedicated to each thread or allocated on
demand, and if there genuinely is a use case for nesting later on, worry
about it then.
So long as the kernel handles a long sequence of sequential emulated
branches gracefully (not necessarily correctly).
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