Re: [PATCH v2 2/3] MIPS: Setup an instruction emulation in VDSO protected page instead of user stack

From: Leonid Yegoshin
Date: Thu Oct 09 2014 - 20:07:41 EST

On 10/09/2014 04:40 PM, James Hogan wrote:

It may be a case for mix of FPU and MIPS R6 emulations. I just keep both
emulators separate as much as possible but I assume that without prove
it may be stackable - some rollback is needed to join both and it may
(probably) cause a double emulation setup - dsemul may be called twice
for the same pair of instructions. I didn't see that yet, honestly and
you may be right.
If the only time they're used is for emulation of a branch delay slot
instruction which should never be another branch, and signals always
undo the emuframe before being handled (btw, should the BD bit in cause
get set if rewinding for signal handlers/gdb?), then it stands to reason
it should never nest.

I don't want to give a chance. If it is proved excessive, then slashing it - 15minutes, it doesn't harm.

OK, I will spend some time to look into that, it have sense to reconsider after unwinding signals.

You could then avoid the whole stack and per-thread thing and just have
a maximum of one emuframe dedicated to each thread or allocated on
demand, and if there genuinely is a use case for nesting later on, worry
about it then.

As I understand, you propose to allocate some space in mmap.

This requires a stuff to handle allocation of user space beyond VMAs.
It also may have some pain during thread creation, stopping and subsequent cloning because that memory allocator should service that events too and it may be not easy if emulation blocks are packed into page. If it is not packed then it waste of user space and put additional constraint to number of thread on single mmap.

Some cooperation with GLIBC may be needed to prevent re-use of user address space, at a moment not sure the extent of it.

I estimated that it can be much more troubling.

So long as the kernel handles a long sequence of sequential emulated
branches gracefully (not necessarily correctly).

I don't understand a question. Each pair/single instruction is emulated separately but there is some pipeline of that, even in FPU emulator, it is just not this patch issue.

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