[PATCH 11/15] dt: binding: add binding for TZ1090 PDC clock

[James Hogan]

The TZ1090 PDC (PowerDown Controller) clock should be at 32.768KHz, and
is generated either directly from the XTAL3 clock or by dividing the
XTAL1 clock. Both the divide and the mux are in a single register which
also contains GPIO output data, and may need to be used by other
non-Linux cores and threads, so create a special clock binding for this
clock.

It essentially has just two clock inputs, and two clock outputs.

Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx>
Cc: Mike Turquette <mturquette@xxxxxxxxxx>
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Pawel Moll <pawel.moll@xxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Cc: Ian Campbell <ijc+devicetree@xxxxxxxxxxxxxx>
Cc: Kumar Gala <galak@xxxxxxxxxxxxxx>
Cc: linux-metag@xxxxxxxxxxxxxxx
Cc: devicetree@xxxxxxxxxxxxxxx
---
 .../bindings/clock/img,tz1090-pdc-clock.txt        | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/img,tz1090-pdc-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/img,tz1090-pdc-clock.txt b/Documentation/devicetree/bindings/clock/img,tz1090-pdc-clock.txt
new file mode 100644
index 0000000..68e2eee
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/img,tz1090-pdc-clock.txt
@@ -0,0 +1,44 @@
+Binding for TZ1090 PDC clock.
+
+This binding uses the common clock binding[1]. It has two input clocks
+(clocks[0..1]), two output clocks (out[0..1]), and a memory-mapped register
+(reg) controlling a divider and a mux atomically with respect to other fields
+and (non-Linux) threads or cores.
+
+              _____
+clocks[0] ___| div |______________________
+             |_____|  |    ____   out[0]
+                      `--o| sw \__________
+clocks[1] ----------------|____/  out[1]
+
+
+out[0] = clocks[0] / (reg[26:16] + 1)
+out[1] = reg[30] ? clocks[1] : out[0]
+
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible         : shall be "img,tz1090-pdc-clock".
+- #clock-cells       : from common clock binding; shall be set to 1.
+- reg                : base address for register controlling mux and divider
+- clocks             : clock specifiers of two parent clocks
+- clock-output-names : from common clock binding. Name of two output clocks.
+
+Clock Specifier Definition:
+- <1st-cell>: output clock number.
+
+Examples:
+	/*           ___________
+	 * xtal1 ___| xtal1_div |____________________________
+	 *          |___________|  |    ________   xtal1_div
+	 *                         `--o| rtc_sw \____________
+	 * xtal3 ----------------------|________/  32khz
+	 */
+	pdc_clk {
+		compatible = "img,tz1090-pdc-clock";
+		#clock-cells = <1>;
+		reg = <0x02006500 4>;	/* SOC_GPIO_CONTROL0 */
+		clocks = <&xtal1>, <&xtal3>;
+		clock-output-names = "xtal1_div", "32khz";
+	};
-- 
2.0.4

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