Re: [PATCH V4 08/16] irqchip: Add new driver for BCM7038-style level 1 interrupt controllers

[Kevin Cernekee]

On Mon, Dec 1, 2014 at 8:09 AM, Jonas Gorski <jogo@xxxxxxxxxxx> wrote:
> I'm not that firm in interrupt controller terminology, but can this be
> a level 1 interrupt controller if it has a parent interrupt
> controller? Isn't the parent the level 1 interrupt controller? Or
> would the parent then be a level 0 interrupt controller? ;-)

According to the register manual, this is an L1 controller and the
"IRQ0" controller handled by irq-bcm7120-l2.c is an L2 controller.

This terminology is used consistently across the MIPS and ARM STB
chips, but it is worth noting that MIPS has a builtin "L0 controller"
(not a published term) to demux the 5 HW IRQ lines, while ARM only
uses a single IRQ input for peripherals.  On STB MIPS platforms it is
typical to only use one HW IRQ input per CPU (TP).

Also note that brcm,bcm3384-l2-intc can either be used for an L1
(PERIPH INT block) or an L2/L3 (ZMIPS/CMIPS/IOP).
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