Re: [PATCH V6 4/6] perf, x86: handle multiple records in PEBS buffer

[Peter Zijlstra]

On Fri, Apr 17, 2015 at 12:50:33PM +0000, Liang, Kan wrote:
> 
> 
> > >
> > >  A) the CTRn value reaches 0:
> > >     - the corresponding bit in GLOBAL_STATUS gets set
> > >     - we start arming the hardware assist
> > >
> > >     < some unspecified amount of time later --
> > >         this could cover multiple events of interest >
> > >
> > >  B) the hardware assist is armed, any next event will trigger it
> > >
> > >  C) a matching event happens:
> > >     - the hardware assist triggers and generates a PEBS record
> > >       this includes a copy of GLOBAL_STATUS at this moment
> > >     - if we auto-reload we (re)set CTRn
> > 
> > Is this actually true? Do we reload here or on A ?
> > 
> 
> Yes, on C.
> According to SDM Volume 3, 18.7.1.1, the reset value will be
> loaded after each PEBS record is written, which is done
> by hw assist.

OK, then I did indeed remember that right.

But that brings us to patch 1 of this series, how is that correct in the
face of this? There is an arbitrary delay (A->B) added to the period.
And the Changelog of course never did bother to make that clear.
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