Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
From: Tim Chen
Date: Thu Aug 20 2015 - 11:03:35 EST
On Thu, 2015-08-20 at 06:08 +0200, Borislav Petkov wrote:
> On Wed, Aug 19, 2015 at 09:49:58AM -0700, Tim Chen wrote:
> > Mouli did the patch originally but he left the company. So
> > I'm picking it up.
>
> So the SOB chain should be:
>
> From: you
>
> <commit message>
>
> Originally-by: Mouli
> Signed-off-by: you
>
Thanks. Revised patch embedded below.
Tim
--->8---
From: Tim Chen <tim.c.chen@xxxxxxxxxxxxxxx>
Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
The Intel Secure Hash Algorithm Extensions are designed to improve the performance
of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit.
This will allow the feature to be shown in the /proc/cpuinfo.
The SHA extension programming guide is found in chapter 8 of the Intel
Architecture Instruction Set Extensions Programming reference:
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf
Originally-by: Chandramouli Narayanan <mouli@xxxxxxxxxxxxxxx>
Signed-off-by: Tim Chen <tim.c.chen@xxxxxxxxxxxxxxx>
---
arch/x86/include/asm/cpufeature.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 3d6606f..a94f83d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -239,6 +239,7 @@
#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
+#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
--
1.8.3.1
--
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