[PATCH v2 2/2] mtd: spi-nor: add new device MT35X

From: Karl Zhang
Date: Sun Dec 13 2015 - 20:57:38 EST


Micron has announced a new SPI NOR device MT35X(XTRMFlash).
The device can support x1 or x8 bus I/O for high speed.

This patch is purpose to add MT35X into the arch, only
extended mode (x1) was enabled. Octal mode I/O will be done
in the futrue.

Signed-off-by: Karl Zhang <karlzhang@xxxxxxxxxx>
---
v2: remove change line for m25p_ids[]

drivers/mtd/spi-nor/spi-nor.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3b2460e..34686b5 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -192,6 +192,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,

switch (JEDEC_MFR(info)) {
case SNOR_MFR_MICRON:
+ case SNOR_MFR_MICRON_JEDEC:
/* Some Micron need WREN command; all will accept it */
need_wren = true;
case SNOR_MFR_MACRONIX:
@@ -756,6 +757,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+ { "mt35x512", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR) },

/* PMC */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
--
1.9.1

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