Re: [RFC PATCH] Add IPI entry for CPU UP

[Mark Rutland]

On Mon, Jan 11, 2016 at 10:55:08AM +0000, Zhaoyang Huang (éæé) wrote:
> 
> ________________________________________
> From: Catalin Marinas <catalin.marinas@xxxxxxx>
> Sent: Monday, January 11, 2016 6:06 PM
> To: Lorenzo Pieralisi
> Cc: Zhaoyang Huang; Zhaoyang Huang (éæé); will.deacon@xxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; hanjun.guo@xxxxxxxxxx; suzuki.poulose@xxxxxxx; Mark Rutland
> Subject: Re: [RFC PATCH] Add IPI entry for CPU UP
> 
> On Mon, Jan 11, 2016 at 09:59:25AM +0000, Lorenzo Pieralisi wrote:
> > On Mon, Jan 11, 2016 at 03:10:40PM +0800, Zhaoyang Huang wrote:
> > > In some ARM SOCs, IPI interrupt is used for hotplug in one cpu, that is,
> > > sending a IPI to the core in WFI and powerdown status. So Add a IPI
> > > entry for handle this kind of cpu up interrupt
> >
> > On arm64 SOCs, with a mainline kernel, you can only hotplug CPUs out
> > and back in by using the PSCI firmware interface, which does not
> > require an IPI to boot a CPU, therefore this patch is useless.
> 
> I fully agree.
> 
> BTW, such patches should cc linux-arm-kernel@xxxxxxxxxxxxxxxxxxx as well
> since they are ARM related.
> 
> Hi both,
> In fact, this patch is related to the counterpart of the PSCI code in
> kernel world which you mentioned before. In SPRD's SOC, we have to
> implement a way of "wakeup" the core in powerdown state, which is to
> launch a IPI to the dest core.

This is not required with PSCI, which abstracts the wakeup and power
management behind the CPU_ON call.

The kernel should only have to issue a CPU_ON call, and the firmware
should do the right thing behind the scenes (e.g. enabling power to the
core, sending an IPI if necessary).

If the kernel needs to do anything other than issue a CPU_ON call, this
is not PSCI.

> The reason why we can not accessing power related register to light on
> the core is the state machine of the PMU will not be safe for this
> scenario.

I'm not sure I understand.

Which software agent (kernel? firmware?) cannot access this PMU
register, and why?

What is the problem with the PMU state machine?

Thanks,
Mark.