Re: [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed

From: Heiko Stübner
Date: Sun Mar 27 2016 - 17:27:12 EST

Am Samstag, 26. März 2016, 14:37:53 schrieb Xing Zheng:
> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL,
> there is incorrect to select bit_0 and bit_1 as the main and alternate
> parents for LPLL/BPLL. They should be configurable.
> Signed-off-by: Xing Zheng <zhengxing@xxxxxxxxxxxxxx>

I've folded this fix into the original patch [0]