Re: [PATCH -v2 4/6] locking, arch: Update spin_unlock_wait()

[Chris Metcalf]

On 5/27/2016 5:05 AM, Peter Zijlstra wrote:
> On Thu, May 26, 2016 at 05:10:36PM -0400, Chris Metcalf wrote:
> > On 5/26/2016 10:19 AM, Peter Zijlstra wrote:
> > > --- a/arch/tile/lib/spinlock_32.c
> > > +++ b/arch/tile/lib/spinlock_32.c
> > > @@ -72,10 +72,14 @@ void arch_spin_unlock_wait(arch_spinlock
> > >   	if (next == curr)
> > >   		return;
> > > +	smp_rmb();
> > > +
> > >   	/* Wait until the current locker has released the lock. */
> > >   	do {
> > >   		delay_backoff(iterations++);
> > >   	} while (READ_ONCE(lock->current_ticket) == curr);
> > > +
> > > +	smp_acquire__after_ctrl_dep();
> > >   }
> > >   EXPORT_SYMBOL(arch_spin_unlock_wait);
> > > --- a/arch/tile/lib/spinlock_64.c
> > > +++ b/arch/tile/lib/spinlock_64.c
> > > @@ -72,10 +72,14 @@ void arch_spin_unlock_wait(arch_spinlock
> > >   	if (arch_spin_next(val) == curr)
> > >   		return;
> > > +	smp_rmb();
> > > +
> > >   	/* Wait until the current locker has released the lock. */
> > >   	do {
> > >   		delay_backoff(iterations++);
> > >   	} while (arch_spin_current(READ_ONCE(lock->lock)) == curr);
> > > +
> > > +	smp_acquire__after_ctrl_dep();
> > >   }
> > >   EXPORT_SYMBOL(arch_spin_unlock_wait);
> > The smp_rmb() are unnecessary for tile.  We READ_ONCE next/curr from the
> > lock and compare them, so we know the load(s) are complete.  There's no
> > microarchitectural speculation going on so that's that.  Then we READ_ONCE
> > the next load on the lock from within the wait loop, so our load/load
> > ordering is guaranteed.
> Does TILE never speculate reads? Because in that case the control
> dependency already provides a full load->load,store barrier and you'd
> want smp_acquire__after_ctrl_dep() to be a barrier() instead of
> smp_rmb().

Yes, that's a good point.  I didn't look at the definition of smp_acquire__after_ctrl_dep(),
but it certainly sounds like that's exactly a compiler barrier for tile.  There is no load
speculation performed.  The only out-of-order stuff that happens is in the memory
subsystem: stores will become visible in arbitrary order, and loads will arrive in
arbitrary order, but as soon as the result of a load is used in any other kind of
instruction, the instruction issue will halt until the pending load(s) for the instruction
operands are available.

--
Chris Metcalf, Mellanox Technologies
http://www.mellanox.com