Re: [v2 1/7] x86/mpx: Do not use SIB index if index points to R/ESP

[Ricardo Neri]

On Fri, 2016-12-23 at 17:57 -0800, Andy Lutomirski wrote:
> On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri
> <ricardo.neri-calderon@xxxxxxxxxxxxxxx> wrote:
> > Section 2.2.1.2 of the Intel 64 and IA-32 Architectures Software
> > Developer's Manual volume 2A states that when memory addressing is used
> > (i.e., mod part of ModR/M is not 3), a SIB byte is used and the index of
> > the SIB byte points to the R/ESP (i.e.,index = 4), the index should not be
> > used in the computation of the memory address.
> >
> > An example of such instruction could be
> >
> >     insn -0x80(%rsp)
> >
> > This is represented as:
> >
> >      [opcode] 4c 24 80
> >
> >       ModR/M: mod: 1, reg: 1: r/m: 4 (R/ESP)
> >       SIB 24: sc: 0, index: 100 (R/ESP), base(R/ESP): 100
> >       Displacement -0x80
> >
> > The correct address is (base) + displacement; no index is used.
> >
> > Care is taken to allow R12 to be used as index, which is a valid scenario.
> 
> Since I have no idea what this patch has to do with the rest of the
> series, I'll ask a question:

Thanks for your feedback! I saw in a previous e-mail that you read the
cover-letter. :)
> 
> Why isn't this code in the standard x86 instruction decoder?  Is the
> decoder similarly buggy?

I did not find any bug in the instruction decoder. I think the reason
this code is not in the decoder is that the decoder only gives you the
bytes of the instructions without any meaning. For instance, it gives
you the ModRM byte but it does not tell you what register or addressing
mode is used.

To fully emulate the UMIP instructions I need to give meaning to the
ModRM and SIB bytes. Since I was trying many operand combinations, I ran
into this issue.

Thanks and BR,
Ricardo