Re: [PATCH RFC 0/4] 5-level EPT

[Valdis . Kletnieks]

On Thu, 29 Dec 2016 17:25:59 +0800, Liang Li said:
> x86-64 is currently limited physical address width to 46 bits, which
> can support 64 TiB of memory. Some vendors require to support more for
> some use case. Intel plans to extend the physical address width to
> 52 bits in some of the future products.

Can you explain why this patchset mentions 52 bits in some places,
and 57 in others?  Is it because there are currently in-process
chipsets that will do 52, but you want to future-proof it by extending
it to 57 so future chipsets won't need more work?  Or is there some other
reason?

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