Re: [PATCH v2] edac, i5000, i5400: fix definition of nrecmemb register

[Borislav Petkov]

On Wed, Jun 28, 2017 at 08:57:29PM -0400, JÃrÃmy Lefaure wrote:
> In i5000 and i5400 edac drivers, the register nrecmemb is defined as a
> 16 bits value which result in wrong shifts in the code:
>   CHECK   drivers/edac/i5000_edac.c
> drivers/edac/i5000_edac.c:485:15: warning: right shift by bigger than
> source value
> drivers/edac/i5000_edac.c:580:23: warning: right shift by bigger than
> source value
>   CC      drivers/edac/i5000_edac.o
>   CHECK   drivers/edac/i5400_edac.c
> drivers/edac/i5400_edac.c:391:36: warning: right shift by bigger than
> source value
> drivers/edac/i5400_edac.c:401:37: warning: right shift by bigger than
> source value
>   CC      drivers/edac/i5400_edac.o
> 
> In the datasheets ([1], section 3.9.22.20 and [2], section 3.9.22.21),
> this register is a 32 bits register. A u32 value for the register fixes
> the wrong shifts warnings and matches the datasheet.
> 
> This patch also fixes the mask to access to the CAS bits [27:16] in
> the i5000 edac driver.
> 
> [1]: https://www.intel.com/content/dam/doc/datasheet/5000p-5000v-5000z-chipset-memory-controller-hub-datasheet.pdf
> [2]: https://www.intel.se/content/dam/doc/datasheet/5400-chipset-memory-controller-hub-datasheet.pdf
> 
> Signed-off-by: JÃrÃmy Lefaure <jeremy.lefaure@xxxxxxxxxxxx>
> ---
> 
> I have found this error thanks to the sparse tool. Please note that this patch
> hasn't been tested on real hardware.
> 
> v2:
> * fix mask in NREC_CAS macro (0xFFF instead of 0x1FFF)
> * fix bits description ("[27:16] instead of "[16 to 28]") in commit message
> 
> 
>  drivers/edac/i5000_edac.c | 6 +++---
>  drivers/edac/i5400_edac.c | 4 ++--
>  2 files changed, 5 insertions(+), 5 deletions(-)

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

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