Re: [PATCH v4 00/10] PCID and improved laziness
From: Andy Lutomirski
Date: Tue Jul 11 2017 - 11:01:19 EST
On Tue, Jul 11, 2017 at 4:32 AM, Matt Fleming <matt@xxxxxxxxxxxxxxxxxxx> wrote:
> On Fri, 30 Jun, at 01:44:22PM, Matt Fleming wrote:
>> On Thu, 29 Jun, at 08:53:12AM, Andy Lutomirski wrote:
>> > *** Ingo, even if this misses 4.13, please apply the first patch before
>> > *** the merge window.
>> > There are three performance benefits here:
>> > 1. TLB flushing is slow. (I.e. the flush itself takes a while.)
>> > This avoids many of them when switching tasks by using PCID. In
>> > a stupid little benchmark I did, it saves about 100ns on my laptop
>> > per context switch. I'll try to improve that benchmark.
>> > 2. Mms that have been used recently on a given CPU might get to keep
>> > their TLB entries alive across process switches with this patch
>> > set. TLB fills are pretty fast on modern CPUs, but they're even
>> > faster when they don't happen.
>> > 3. Lazy TLB is way better. We used to do two stupid things when we
>> > ran kernel threads: we'd send IPIs to flush user contexts on their
>> > CPUs and then we'd write to CR3 for no particular reason as an excuse
>> > to stop further IPIs. With this patch, we do neither.
>> Heads up, I'm gonna queue this for a run on SUSE's performance test
> FWIW, I didn't see any change in performance with this series on a
> PCID-capable machine. On the plus side, I didn't see any weird-looking
> bugs either.
> Are your benchmarks available anywhere?
$ ./context_switch_latency_64 0 process same
$ ./madvise_bounce_64 10k [IIRC -- it might have been a different loop count]