RE: [PATCH RFC 5/5] Add KSZ8795 SPI driver
From: Tristram.Ha
Date: Fri Sep 08 2017 - 13:36:51 EST
> -----Original Message-----
> From: Pavel Machek [mailto:pavel@xxxxxx]
> Sent: Friday, September 08, 2017 2:26 AM
> To: Tristram Ha - C24268
> Cc: andrew@xxxxxxx; muvarov@xxxxxxxxx; nathan.leigh.conrad@xxxxxxxxx;
> vivien.didelot@xxxxxxxxxxxxxxxxxxxx; f.fainelli@xxxxxxxxx;
> netdev@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Woojung Huh - C21699
> Subject: Re: [PATCH RFC 5/5] Add KSZ8795 SPI driver
>
> Hi!
>
>
> > +static int ksz_spi_read(struct ksz_device *dev, u32 reg, u8 *data,
> > + unsigned int len)
> > +{
> > + struct spi_device *spi = dev->priv;
> > +
> > + return ksz_spi_read_reg(spi, reg, data, len); }
> > +
> > +static int ksz_spi_read8(struct ksz_device *dev, u32 reg, u8 *val) {
> > + return ksz_spi_read(dev, reg, val, 1); }
> > +
> > +static int ksz_spi_read16(struct ksz_device *dev, u32 reg, u16 *val) {
> > + int ret = ksz_spi_read(dev, reg, (u8 *)val, 2);
> > +
> > + if (!ret)
> > + *val = be16_to_cpu(*val);
> > +
> > + return ret;
> > +}
>
> > +static int ksz_spi_read32(struct ksz_device *dev, u32 reg, u32 *val) {
> > + int ret = ksz_spi_read(dev, reg, (u8 *)val, 4);
> > +
> > + if (!ret)
> > + *val = be32_to_cpu(*val);
> > +
> > + return ret;
> > +}
>
> Please format according to CodingStyle. (Not only this.)
>
> And this will be common for more drivers. Can it go to a header file
> and be included...?
>
Sorry about the formatting. It seems my e-mail system needs to be checked
to make sure it does not auto-format the contents again.
About the SPI access functions they are the same for each driver except the
low level ksz_spi_read_reg and ksz_spi_write_reg. The dev_io_ops structure
should contain only those 2 and ksz_spi_get and ksz_spi_set.
But that requires changing ksz_spi.c. The idea was to keep the code of
KSZ9477 driver with little change as possible while introducing another driver.
The KSZ9477 driver will need to be updated with some of the code in KSZ8795
driver regarding port membership and MIB counter reading.