Re: [PATCH v6 05/11] x86: add SGX MSRs to msr-index.h

[Sean Christopherson]

On Sat, 2017-11-25 at 21:29 +0200, Jarkko Sakkinen wrote:
> From: Haim Cohen <haim.cohen@xxxxxxxxx>
> 
> These MSRs hold the SHA256 checksum of the currently configured root
> key for enclave signatures.

The commit message doesn't talk about the launch control bit in the
feature control MSR.

> 
> Signed-off-by: Haim Cohen <haim.cohen@xxxxxxxxx>
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@xxxxxxxxxxxxxxx>
> ---
> Âarch/x86/include/asm/msr-index.h | 7 +++++++
> Â1 file changed, 7 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index b35cb98b5d60..22e27d46d046 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -436,6 +436,7 @@
> Â#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
> Â#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)
> Â#define FEATURE_CONTROL_SGX_ENABLEÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ(1<<18)
> +#define FEATURE_CONTROL_SGX_LAUNCH_CONTROL_ENABLE	(1<<17)
> Â#define FEATURE_CONTROL_LMCE				(1<<20)
> Â
> Â#define MSR_IA32_APICBASE		0x0000001b
> @@ -502,6 +503,12 @@
> Â#define PACKAGE_THERM_INT_LOW_ENABLE		(1 << 1)
> Â#define PACKAGE_THERM_INT_PLN_ENABLE		(1 << 24)
> Â
> +/* Intel SGX MSRs */
> +#define MSR_IA32_SGXLEPUBKEYHASH0	0x0000008C
> +#define MSR_IA32_SGXLEPUBKEYHASH1	0x0000008D
> +#define MSR_IA32_SGXLEPUBKEYHASH2	0x0000008E
> +#define MSR_IA32_SGXLEPUBKEYHASH3	0x0000008F
> +
> Â/* Thermal Thresholds Support */
> Â#define THERM_INT_THRESHOLD0_ENABLEÂÂÂÂ(1 << 15)
> Â#define THERM_SHIFT_THRESHOLD0ÂÂÂÂÂÂÂÂ8