Re: [RFC PATCH v10 6/7] PCI / PM: Move acpi wakeup code to pci core

[Rafael J. Wysocki]

On Fri, Dec 8, 2017 at 5:37 PM, Tony Lindgren <tony@xxxxxxxxxxx> wrote:
> * Brian Norris <briannorris@xxxxxxxxxxxx> [171207 00:32]:
>> On Wed, Dec 06, 2017 at 04:17:54PM -0800, Tony Lindgren wrote:
>> > * Brian Norris <briannorris@xxxxxxxxxxxx> [171206 19:36]:
>> > > By the way, it seems pretty ambiguous how we want to handle things like
>> > > (a) multiple devices sharing the same WAKE#
>> > > (b) systems where a slot is swappable
>> > >
>> > > For (a), the main problem is that if we have to repeat the interrupt
>> > > definition in multiple devices, then we have to deal with something like
>> > > IRQF_SHARED. That can be done, but it makes it much harder to use the
>> > > dedicated wakeirq helpers.
>> >
>> > This will get messy, let's not go there :) That is unless the hardware
>> > really has a single interrupt wired to multiple devices. And in that
>> > case almost certainly a custom interrupt handler is needed.
>>
>> As Rafael mentioned, the spec doesn't clearly delineate a required
>> hierarchy to the WAKE# pin, and it's certainly possible to share it. I'm
>> fine dodging that question for now, and only writing said custom
>> interrupt handler if/when needed.
>
> OK if the WAKE# pin is shared then PCI (or hardware specific?) code needs
> to figure out from where it came from.

Right.

Basically, that would need a list (or equivalent) of devices sharing
the wakeup IRQ and if that triggers, it needs to walk the list and
call pci_pme_wakeup() for all devices in it.

>> But device tree bindings are "forever", so it seems reasonable to at
>> least agree how it should be defined.
>
> Well that's why we're just using the existing interrupts-extended
> binding there :) It does not leave out the option for shared interrupts,
> it's just that drivers/base/power/wakeirq.c can't deal with them in a
> sane way or at least we'd have to add a flag to not enable/disable the
> wakeirq automatically.

I think that the binding needs to be sort-of PCI-specific to cover the
shared case.

I'm not sure if there are any other buses needing that (they would
need to define standard PM registers as PCI does).