Re: [PATCH v2 05/19] pinctrl: sh-pfc: Initial R-Car M3-N support

From: Geert Uytterhoeven
Date: Tue Feb 20 2018 - 13:35:57 EST


Hi Jacopo,

On Tue, Feb 20, 2018 at 4:12 PM, Jacopo Mondi <jacopo+renesas@xxxxxxxxxx> wrote:
> Add initial PFC support for R-Car M3-N (r8a77965) SoC.
> No groups or functions defined, just pin and registers enumeration.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@xxxxxxxxxx>
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
>
> ---
> v1 -> v2:
>
> Applied the following patches for r8a7796 on r8a77965:
>
> commit 0f4713d71f22d3b0ec3de6ae4a126cceecdea82b
> Author: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> Date: Thu Nov 16 23:59:21 2017 +0900
> pinctrl: sh-pfc: r8a7796: Rename RTS{0,1,3,4}# pin function definitions
>
> commit fbd81e345c9393b96e8ad252eef390f8c6f9cf60
> Author: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> Date: Thu Nov 16 12:17:18 2017 +0900
> pinctrl: sh-pfc: r8a7796: Fix to delete A20..A25 pins function definitions

Thanks for the update!

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
and queueing in sh-pfc-for-v4.17, with the following recent fixes for
r8a7796 that are also applicable to r8a77965 folded in:

pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin
assignment for NDFC pins group
pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for
SSI pins group

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds