[tip:locking/core] memory-barriers: Fix description of data dependency barriers

[tip-bot for Nikolay Borisov]

Commit-ID:  51de78892b1294d1521c41226a5ef215a910c25f
Gitweb:     https://git.kernel.org/tip/51de78892b1294d1521c41226a5ef215a910c25f
Author:     Nikolay Borisov <nborisov@xxxxxxxx>
AuthorDate: Tue, 20 Feb 2018 15:25:08 -0800
Committer:  Ingo Molnar <mingo@xxxxxxxxxx>
CommitDate: Wed, 21 Feb 2018 09:58:14 +0100

memory-barriers: Fix description of data dependency barriers

In the description of data dependency barriers the words 'before' is
used erroneously. Since such barrier order dependent loads one after
the other. So substitute 'before' with 'after'.

Signed-off-by: Nikolay Borisov <nborisov@xxxxxxxx>
Signed-off-by: Paul E. McKenney <paulmck@xxxxxxxxxxxxxxxxxx>
Acked-by: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: akiyks@xxxxxxxxx
Cc: boqun.feng@xxxxxxxxx
Cc: dhowells@xxxxxxxxxx
Cc: j.alglave@xxxxxxxxx
Cc: linux-arch@xxxxxxxxxxxxxxx
Cc: luc.maranget@xxxxxxxx
Cc: npiggin@xxxxxxxxx
Cc: parri.andrea@xxxxxxxxx
Cc: stern@xxxxxxxxxxxxxxxxxxx
Cc: will.deacon@xxxxxxx
Link: http://lkml.kernel.org/r/1519169112-20593-8-git-send-email-paulmck@xxxxxxxxxxxxxxxxxx
Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
---
 Documentation/memory-barriers.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index a37d3af..da6525b 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -403,7 +403,7 @@ Memory barriers come in four basic varieties:
      where two loads are performed such that the second depends on the result
      of the first (eg: the first load retrieves the address to which the second
      load will be directed), a data dependency barrier would be required to
-     make sure that the target of the second load is updated before the address
+     make sure that the target of the second load is updated after the address
      obtained by the first load is accessed.
 
      A data dependency barrier is a partial ordering on interdependent loads