RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Andy Tang]

Hi Scott,

Please see my replay inline.

> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@xxxxxxxxxxxxxxxxxxx>
> On Behalf Of Scott Wood
> Sent: 2018年8月31日 1:43
> To: Vabhav Sharma <vabhav.sharma@xxxxxxx>;
> linux-kernel@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx;
> linuxppc-dev@xxxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; rjw@xxxxxxxxxxxxx;
> viresh.kumar@xxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx;
> linux-pm@xxxxxxxxxxxxxxx; linux-kernel-owner@xxxxxxxxxxxxxxx;
> catalin.marinas@xxxxxxx; will.deacon@xxxxxxx;
> gregkh@xxxxxxxxxxxxxxxxxxx; arnd@xxxxxxxx;
> kstewart@xxxxxxxxxxxxxxxxxxx; yamada.masahiro@xxxxxxxxxxxxx
> Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@xxxxxxx>; Andy Tang
> <andy.tang@xxxxxxx>; linux@xxxxxxxxxxxxxxx; Varun Sethi
> <V.Sethi@xxxxxxx>; Udit Kumar <udit.kumar@xxxxxxx>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> lx2160a
> 
> On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> > On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > > -----Original Message-----
> > > > From: linux-kernel-owner@xxxxxxxxxxxxxxx <linux-kernel-
> > > > owner@xxxxxxxxxxxxxxx> On Behalf Of Scott Wood
> > > > Sent: Wednesday, August 29, 2018 5:49 AM
> > > > To: Vabhav Sharma <vabhav.sharma@xxxxxxx>; linux-
> > > > kernel@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> > > > robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx;
> > > > linuxppc-dev@xxxxxxxxxxxxxxxx; linux-arm-
> > > > kernel@xxxxxxxxxxxxxxxxxxx; mturquette@xxxxxxxxxxxx;
> > > > sboyd@xxxxxxxxxx; rjw@xxxxxxxxxxxxx; viresh.kumar@xxxxxxxxxx;
> > > > linux-clk@xxxxxxxxxxxxxxx; linux-pm@xxxxxxxxxxxxxxx;
> > > > linux-kernel-owner@xxxxxxxxxxxxxxx;
> > > > catalin.marinas@xxxxxxx; will.deacon@xxxxxxx;
> > > > gregkh@xxxxxxxxxxxxxxxxxxx; arnd@xxxxxxxx;
> > > > kstewart@xxxxxxxxxxxxxxxxxxx; yamada.masahiro@xxxxxxxxxxxxx
> > > > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@xxxxxxx>; Andy
> Tang
> > > > <andy.tang@xxxxxxx>; Udit Kumar <udit.kumar@xxxxxxx>;
> > > > linux@xxxxxxxxxxxxxxx; Varun Sethi <V.Sethi@xxxxxxx>
> > > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support
> > > > for lx2160a
> > > >
> > > > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > > > From: Yogesh Gaur <yogeshnarayan.gaur@xxxxxxx>
> > > > >
> > > > > Add clockgen support for lx2160a.
> > > > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > > > >
> > > > > Signed-off-by: Tang Yuantian <andy.tang@xxxxxxx>
> > > > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@xxxxxxx>
> > > > > Signed-off-by: Vabhav Sharma <vabhav.sharma@xxxxxxx>
> > > > > ---
> > > > >  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
> > > > >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> > > > >  2 files changed, 14 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> > > > > index
> > > > > 3a1812f..fc6e308 100644
> > > > > --- a/drivers/clk/clk-qoriq.c
> > > > > +++ b/drivers/clk/clk-qoriq.c
> > > > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo {  };
> > > > >
> > > > >  #define NUM_HWACCEL	5
> > > > > -#define NUM_CMUX	8
> > > > > +#define NUM_CMUX	16
> > > > >
> > > > >  struct clockgen;
> > > > >
> > > > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo
> > > > > chipinfo[] = {
> > > > >  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > >  	},
> > > > >  	{
> > > > > +		.compat = "fsl,lx2160a-clockgen",
> > > > > +		.cmux_groups = {
> > > > > +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > > > +		},
> > > > > +		.cmux_to_group = {
> > > > > +			0, 0, 0, 0, 1, 1, 1, 1, -1
> > > > > +		},
> > > > > +		.pll_mask = 0x37,
> > > > > +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > > +	},
> > > >
> > > > Why are you increasing NUM_CMUX beyond 8 for a chip that only
> has
> > > > 8 entries in cmux_to_group?
> > >
> > > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> >
> > So?  This is about cmuxes, not cores.  You're increasing the array
> > without ever using the new size.
> 
> Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator,
> because the array was of length 8.  Probably the array should be changed
> to NUM_CMUX+1 so every array can be -1 terminated.
> 
[Andy] How about we add -1 terminator to p4080 and increase NUM_CMUX to 16?
We don't want to increase NUM_CMUX each time new soc with more cmuxes added.

BR,
Andy Tang

> -Scott
> 
> 
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