Re: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver

[Anup Patel]

On Mon, Sep 10, 2018 at 9:43 PM, Christoph Hellwig <hch@xxxxxxxxxxxxx> wrote:
> On Mon, Sep 10, 2018 at 07:59:15PM +0530, Anup Patel wrote:
>> > Yes.  external is chained and IPI is still handled explicitly.
>>
>> On riscv64, there are 64 local interrupts (i.e. per-CPU interrupts).
>
> There aren't.  There are 9 right now, which are your three below:

You are thinking very much in-context of SiFive CPUs only.

Lot of SOC vendors are trying to come-up with their own CPUs
and RISC-V spec does not restrict the use of local interrupts.

The mie/mip/sie/sip/uie/uip are all machine word size so on
riscv64 we can theoretically have maximum 64 local interrupts.

>
>> Three of these local interrupts have clearly defined use:
>> 1. Software interrupt (inter-processor interrupt)
>> 2. External interrupt (interrupt from PLIC)
>> 3. Timer interrupt (interrupt from per-CPU timer)
>
> multiplied by 3 for machine, supervisor, user.

Yes, 3 per-CPU interrupts for each CPU mode which
makes it 9 per-CPU interrupts.

In fact, initial intention was to have these separate for
each mode but there is not restriction as explained by
Andrew Waterman on ISA-DEV:

"One key point is that UIRQ, SIRQ, and MIRQ are just names; the letters
U, S, and M don't actually connote anything about privilege.  UIRQ,
SIRQ, and MIRQ are three different interrupt lines on equal footing.
The prefix letters merely reflect the intended use case.  So only one
version of this description is necessary.  I'll try to rewrite a
version with a few corrections."

>
>> Other local interrupts are available for future use.
>
> The others aren't even defined as other interrupts, but just reserved
> fields.  And only one bit per privilege level would even fit into the
> encoding scheme used right now.

That's how it is implemented on SiFive CPUs.

This does not mean we will not have more per-CPU interrupts
in-future.

Regards,
Anup