Re: [PATCH v3 2/2] spi: Introduce new driver for Qualcomm QuadSPI controller

[Stephen Boyd]

Quoting Ryan Case (2018-09-28 11:19:51)
> On Wed, Sep 26, 2018 at 11:43 PM Stephen Boyd <swboyd@xxxxxxxxxxxx> wrote:
> > Quoting Ryan Case (2018-09-26 13:52:04)
> > > From: Girish Mahadevan <girishm@xxxxxxxxxxxxxx>
> > > +#include <asm/unaligned.h>
> > > +
> > > +#define AHB_MIN_HZ             9600000UL
> >
> > Is this used?
> 
> Nope. Do you want all currently unused defines removed or specifically this
> one? I saw precedent in other drivers for defining registers/flags/values of
> supported but unused functionality so I left these (big endian, DDR, ...).

I guess it's fine but I don't know if it will ever be used so remove it?
I'd leave the others if they help someone know what register bits exist.
That's usually how I handle it.

> 
> 
> > > +       speed_hz = slv->max_speed_hz;
> > > +       if (xfer->speed_hz)
> > > +               speed_hz = xfer->speed_hz;
> > > +
> > > +       ret = clk_set_rate(ctrl->clks[QSPI_CLK_CORE].clk, speed_hz * 4);
> >
> > Why 4? Is that related to the number of wires?
> 
> In normal operation the core clock should be running at 4x the rate of the
> transfer clock regardless of number of wires used.

Ok. Maybe add a comment so we understand that.

> 
> > > +                       put_unaligned(rd_fifo, word_buf++);
> > > +               }
> > > +               ctrl->xfer.rx_buf = word_buf;
> > > +       }
> > > +
> > > +       if (bytes_to_read) {
> > > +               byte_buf = ctrl->xfer.rx_buf;
> >
> > Does this need to move forward by words_to_read bytes so that the left
> > over bytes are tacked onto the end? Or this should be an else if
> > statement?
> 
> When the words block completes it updates the rx_buf location so it is already
> at the correct offset for bytes.
> 

Ok I see. Subtle!