RE: [PATCH 5/6] pci: layerscape: Add the EP mode support.

From: Xiaowei Bao
Date: Thu Nov 08 2018 - 21:51:00 EST

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-----Original Message-----
From: Xiaowei Bao
Sent: 2018å11æ6æ 14:48
To: 'Kishon Vijay Abraham I' <kishon@xxxxxx>; bhelgaas@xxxxxxxxxx; robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; Leo Li <leoyang.li@xxxxxxx>; lorenzo.pieralisi@xxxxxxx; arnd@xxxxxxxx; gregkh@xxxxxxxxxxxxxxxxxxx; M.h. Lian <minghuan.lian@xxxxxxx>; Mingkai Hu <mingkai.hu@xxxxxxx>; Roy Zang <roy.zang@xxxxxxx>; kstewart@xxxxxxxxxxxxxxxxxxx; cyrille.pitchen@xxxxxxxxxxxxxxxxxx; pombredanne@xxxxxxxx; shawn.lin@xxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linuxppc-dev@xxxxxxxxxxxxxxxx
Cc: Jiafei Pan <jiafei.pan@xxxxxxx>
Subject: RE: [PATCH 5/6] pci: layerscape: Add the EP mode support.

Hi Kishonï

-----Original Message-----
From: Kishon Vijay Abraham I <kishon@xxxxxx>
Sent: 2018å11æ6æ 14:07
To: Xiaowei Bao <xiaowei.bao@xxxxxxx>; bhelgaas@xxxxxxxxxx; robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; Leo Li <leoyang.li@xxxxxxx>; lorenzo.pieralisi@xxxxxxx; arnd@xxxxxxxx; gregkh@xxxxxxxxxxxxxxxxxxx; M.h. Lian <minghuan.lian@xxxxxxx>; Mingkai Hu <mingkai.hu@xxxxxxx>; Roy Zang <roy.zang@xxxxxxx>; kstewart@xxxxxxxxxxxxxxxxxxx; cyrille.pitchen@xxxxxxxxxxxxxxxxxx; pombredanne@xxxxxxxx; shawn.lin@xxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linuxppc-dev@xxxxxxxxxxxxxxxx
Cc: Jiafei Pan <jiafei.pan@xxxxxxx>
Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support.

(Removed Niklas as mails to him is bouncing)

Hi,

Please fix your email client. Refer Documentation/process/email-clients.rst

On 05/11/18 2:45 PM, Xiaowei Bao wrote:
>
>
> -----Original Message-----
> From: Kishon Vijay Abraham I <kishon@xxxxxx>
> Sent: 2018å11æ5æ 16:57
> To: Xiaowei Bao <xiaowei.bao@xxxxxxx>; bhelgaas@xxxxxxxxxx;
> robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; Leo Li
> <leoyang.li@xxxxxxx>; lorenzo.pieralisi@xxxxxxx; arnd@xxxxxxxx;
> gregkh@xxxxxxxxxxxxxxxxxxx; M.h. Lian <minghuan.lian@xxxxxxx>; Mingkai
> Hu <mingkai.hu@xxxxxxx>; Roy Zang <roy.zang@xxxxxxx>;
> kstewart@xxxxxxxxxxxxxxxxxxx; cyrille.pitchen@xxxxxxxxxxxxxxxxxx;
> pombredanne@xxxxxxxx; shawn.lin@xxxxxxxxxxxxxx;
> niklas.cassel@xxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linuxppc-dev@xxxxxxxxxxxxxxxx
> Cc: Jiafei Pan <jiafei.pan@xxxxxxx>
> Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support.
>
> Hi,
>
> On 31/10/18 4:08 PM, Xiaowei Bao wrote:
>>
>>
>> -----Original Message-----
>> From: Kishon Vijay Abraham I <kishon@xxxxxx>
>> Sent: 2018å10æ31æ 12:15
>> To: Xiaowei Bao <xiaowei.bao@xxxxxxx>; bhelgaas@xxxxxxxxxx;
>> robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; Leo Li
>> <leoyang.li@xxxxxxx>; lorenzo.pieralisi@xxxxxxx; arnd@xxxxxxxx;
>> gregkh@xxxxxxxxxxxxxxxxxxx; M.h. Lian <minghuan.lian@xxxxxxx>;
>> Mingkai Hu <mingkai.hu@xxxxxxx>; Roy Zang <roy.zang@xxxxxxx>;
>> kstewart@xxxxxxxxxxxxxxxxxxx; cyrille.pitchen@xxxxxxxxxxxxxxxxxx;
>> pombredanne@xxxxxxxx; shawn.lin@xxxxxxxxxxxxxx;
>> niklas.cassel@xxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
>> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
>> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linuxppc-dev@xxxxxxxxxxxxxxxx
>> Cc: Jiafei Pan <jiafei.pan@xxxxxxx>
>> Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support.
>>
>> Hi,
>>
>> On 31/10/18 8:03 AM, Xiaowei Bao wrote:
>>>
>>>
>>> -----Original Message-----
>>> From: Xiaowei Bao
>>> Sent: 2018å10æ26æ 17:19
>>> To: 'Kishon Vijay Abraham I' <kishon@xxxxxx>; bhelgaas@xxxxxxxxxx;
>>> robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; Leo
>>> robh+Li
>>> <leoyang.li@xxxxxxx>; lorenzo.pieralisi@xxxxxxx; arnd@xxxxxxxx;
>>> gregkh@xxxxxxxxxxxxxxxxxxx; M.h. Lian <minghuan.lian@xxxxxxx>;
>>> Mingkai Hu <mingkai.hu@xxxxxxx>; Roy Zang <roy.zang@xxxxxxx>;
>>> kstewart@xxxxxxxxxxxxxxxxxxx; cyrille.pitchen@xxxxxxxxxxxxxxxxxx;
>>> pombredanne@xxxxxxxx; shawn.lin@xxxxxxxxxxxxxx;
>>> niklas.cassel@xxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
>>> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
>>> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linuxppc-dev@xxxxxxxxxxxxxxxx
>>> Cc: Jiafei Pan <jiafei.pan@xxxxxxx>
>>> Subject: RE: [PATCH 5/6] pci: layerscape: Add the EP mode support.
>>>
>>>
>>>
>>> -----Original Message-----
>>> From: Kishon Vijay Abraham I <kishon@xxxxxx>
>>> Sent: 2018å10æ26æ 13:29
>>> To: Xiaowei Bao <xiaowei.bao@xxxxxxx>; bhelgaas@xxxxxxxxxx;
>>> robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; Leo
>>> robh+Li
>>> <leoyang.li@xxxxxxx>; lorenzo.pieralisi@xxxxxxx; arnd@xxxxxxxx;
>>> gregkh@xxxxxxxxxxxxxxxxxxx; M.h. Lian <minghuan.lian@xxxxxxx>;
>>> Mingkai Hu <mingkai.hu@xxxxxxx>; Roy Zang <roy.zang@xxxxxxx>;
>>> kstewart@xxxxxxxxxxxxxxxxxxx; cyrille.pitchen@xxxxxxxxxxxxxxxxxx;
>>> pombredanne@xxxxxxxx; shawn.lin@xxxxxxxxxxxxxx;
>>> niklas.cassel@xxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
>>> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
>>> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linuxppc-dev@xxxxxxxxxxxxxxxx
>>> Subject: Re: [PATCH 5/6] pci: layerscape: Add the EP mode support.
>>>
>>> Hi,
>>>
>>> On Thursday 25 October 2018 04:39 PM, Xiaowei Bao wrote:
>>>> Add the PCIe EP mode support for layerscape platform.
>>>>
>>>> Signed-off-by: Xiaowei Bao <xiaowei.bao@xxxxxxx>
>>>> ---
>>>> drivers/pci/controller/dwc/Makefile | 2 +-
>>>> drivers/pci/controller/dwc/pci-layerscape-ep.c | 161
>>>> ++++++++++++++++++++++++
>>>> 2 files changed, 162 insertions(+), 1 deletions(-) create mode
>>>> 100644 drivers/pci/controller/dwc/pci-layerscape-ep.c
>>>>
>>>> diff --git a/drivers/pci/controller/dwc/Makefile
>>>> b/drivers/pci/controller/dwc/Makefile
>>>> index 5d2ce72..b26d617 100644
>>>> --- a/drivers/pci/controller/dwc/Makefile
>>>> +++ b/drivers/pci/controller/dwc/Makefile
>>>> @@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
>>>> obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
>>>> obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
>>>> obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
>>>> -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
>>>> +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
>>>> +pci-layerscape-ep.o
>>>> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
>>>> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
>>>> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o diff --git
>>>> a/drivers/pci/controller/dwc/pci-layerscape-ep.c
>>>> b/drivers/pci/controller/dwc/pci-layerscape-ep.c
>>>> new file mode 100644
>>>> index 0000000..3b33bbc
>>>> --- /dev/null
>>>> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
>>>> @@ -0,0 +1,161 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * PCIe controller EP driver for Freescale Layerscape SoCs
>>>> + *
>>>> + * Copyright (C) 2018 NXP Semiconductor.
>>>> + *
>>>> + * Author: Xiaowei Bao <xiaowei.bao@xxxxxxx> */
>>>> +
>>>> +#include <linux/kernel.h>
>>>> +#include <linux/init.h>
>>>> +#include <linux/of_pci.h>
>>>> +#include <linux/of_platform.h>
>>>> +#include <linux/of_address.h>
>>>> +#include <linux/pci.h>
>>>> +#include <linux/platform_device.h> #include <linux/resource.h>
>>>> +
>>>> +#include "pcie-designware.h"
>>>> +
>>>> +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
>>>
>>> The base address should come from dt.
>>>> +
>>>> +struct ls_pcie_ep {
>>>> + struct dw_pcie *pci;
>>>> +};
>>>> +
>>>> +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
>>>> +
>>>> +static bool ls_pcie_is_bridge(struct ls_pcie_ep *pcie) {
>>>> + struct dw_pcie *pci = pcie->pci;
>>>> + u32 header_type;
>>>> +
>>>> + header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
>>>> + header_type &= 0x7f;
>>>> +
>>>> + return header_type == PCI_HEADER_TYPE_BRIDGE; }
>>>> +
>>>> +static int ls_pcie_establish_link(struct dw_pcie *pci) {
>>>> + return 0;
>>>> +}
>>>
>>> There should be some way by which EP should tell RC that it is not configured yet. Are there no bits to control LTSSM state initialization or Configuration retry status enabling?
>>> [Xiaowei Bao] There have not bits to control LTSSM state to tell the RC it is configured. The start link is auto completed.
>>> [Xiaowei Bao] Hi Kishon, is there any advice?
>>
>> If there is no HW support, I don't think anything could be done here. This could result in RC reading configuration space even before EP is fully initialized.
>> [Xiaowei Bao] The bootloader have initialized the EP device and set the config ready bit, and the kernel don't need to do anything.
>
> What does bootloader initalize? The EP driver here will reinitialize everything right?
> [Xiaowei Bao] The bootloader initialize BAR size, outbound window, inbound window and set the config ready bit.

How will bootloader know the BAR size? The BAR size is based on the function driver. How does bootloader configure the OB window? The OB window is configured based on the size and address given by the host dynamically at runtime.

Thanks
Kishon
[Xiaowei Bao] We use the bootloader is u-boot, we implement the EP base feature in the u-boot, e.g.(MEM space access(RC<=>EP), CONFIG space access(RC=>EP)), we set the EP BAR size like kernel(set the PCI_BASE_ADDRESS_n register, but different size), and the outbound windows also be set, and the bar size will be cover by the EP framework driver when kernel start up.
I have to set the dw_pcie_ops, if don't config the dw_pcie_ops there will have call trace, because the DW driver will call the write_dbi or read_dbi function directly but not check the dw_pcie_ops whether is null. I refer to the pcie-designware-plat.c to implement it. I don't know what you said about this, could you tell me the effect, Thanks a lot.

Thanks
Xiaowei
[Xiaowei Bao] Hi Kishon, is there any advice? Thanks.

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