Re: [PATCHv3 2/3] reset: socfpga: add an early reset driver for SoCFPGA

From: Philipp Zabel
Date: Tue Nov 13 2018 - 09:02:39 EST

Hi Dinh,

On Mon, 2018-11-05 at 14:05 -0600, Dinh Nguyen wrote:
> From: Dinh Nguyen <dinh.nguyen@xxxxxxxxx>
>
> Create a separate reset driver that uses the reset operations in
> reset-simple. The reset driver for the SoCFPGA platform needs to
> register early in order to be able bring online timers that needed
> early in the kernel bootup.
>
> We do not need this early reset driver for Stratix10, because on
> arm64, Linux does not need the timers are that in reset. Linux is
> able to run just fine with the internal armv8 timer. Thus, we use
> a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform.
> The Stratix10 platform will continue to use the reset-simple platform
> driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use
> the early reset driver.
>
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---
> v3: use "altr,stratix10-rst-mgr" for Stratix10
> remove "altr,modrst-offset" from reset-simple
> v2: Do not build separate reset driver for STRATIX10
> fix warning: symbol 'socfpga_reset_init' was not declared. Should it be
> static?
> ---
> arch/arm/mach-socfpga/socfpga.c | 4 ++
> drivers/reset/Kconfig | 9 +++-
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-simple.c | 12 +----
> drivers/reset/reset-socfpga.c | 88 +++++++++++++++++++++++++++++++++
> 5 files changed, 103 insertions(+), 11 deletions(-)
> create mode 100644 drivers/reset/reset-socfpga.c
>
> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
> index dde14f7bf2c3..cc64576c102b 100644
> --- a/arch/arm/mach-socfpga/socfpga.c
> +++ b/arch/arm/mach-socfpga/socfpga.c
> @@ -32,6 +32,8 @@ void __iomem *rst_manager_base_addr;
> void __iomem *sdr_ctl_base_addr;
> unsigned long socfpga_cpu1start_addr;
>
> +extern void __init socfpga_reset_init(void);
> +
> void __init socfpga_sysmgr_init(void)
> {
> struct device_node *np;
> @@ -64,6 +66,7 @@ static void __init socfpga_init_irq(void)
>
> if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
> socfpga_init_ocram_ecc();
> + socfpga_reset_init();
> }
>
> static void __init socfpga_arria10_init_irq(void)
> @@ -74,6 +77,7 @@ static void __init socfpga_arria10_init_irq(void)
> socfpga_init_arria10_l2_ecc();
> if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
> socfpga_init_arria10_ocram_ecc();
> + socfpga_reset_init();
> }
>
> static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index c21da9fe51ec..5d7a3ba445aa 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -109,7 +109,7 @@ config RESET_QCOM_PDC
>
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST
> - default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
> + default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
> help
> This enables a simple reset controller driver for reset lines that
> that can be asserted and deasserted by toggling bits in a contiguous,
> @@ -128,6 +128,13 @@ config RESET_STM32MP157
> help
> This enables the RCC reset controller driver for STM32 MPUs.
>
> +config RESET_SOCFPGA
> + bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
> + default ARCH_SOCFPGA && !ARCH_STRATIX10

I don't understand the "&& !ARCH_STRATIX10" part.
Isn't ARCH_SOCFPGA disabled anyway when ARCH_STRATIX10 is enabled?

> + select RESET_SIMPLE
> + help
> + This enables the reset driver for SoCFPGA.
> +
> config RESET_SUNXI
> bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
> default ARCH_SUNXI
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index d08e8b90046a..b14de32eb610 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
> +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
> obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
> diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
> index a91107fc9e27..f2e7a8c1be65 100644
> --- a/drivers/reset/reset-simple.c
> +++ b/drivers/reset/reset-simple.c
> @@ -109,7 +109,7 @@ struct reset_simple_devdata {
> #define SOCFPGA_NR_BANKS 8
>
> static const struct reset_simple_devdata reset_simple_socfpga = {
> - .reg_offset = 0x10,
> + .reg_offset = 0x20,
> .nr_resets = SOCFPGA_NR_BANKS * 32,
> .status_active_low = true,
> };
> @@ -120,7 +120,7 @@ static const struct reset_simple_devdata reset_simple_active_low = {
> };
>
> static const struct of_device_id reset_simple_dt_ids[] = {
> - { .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
> + { .compatible = "altr,stratix10-rst-mgr","altr,rst-mgr", .data = &reset_simple_socfpga },

checkpatch.pl complains about missing whitespace and a long line here.

> { .compatible = "st,stm32-rcc", },
> { .compatible = "allwinner,sun6i-a31-clock-reset",
> .data = &reset_simple_active_low },
> @@ -166,14 +166,6 @@ static int reset_simple_probe(struct platform_device *pdev)
> data->status_active_low = devdata->status_active_low;
> }
>
> - if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
> - of_property_read_u32(dev->of_node, "altr,modrst-offset",
> - &reg_offset)) {
> - dev_warn(dev,
> - "missing altr,modrst-offset property, assuming 0x%x!\n",
> - reg_offset);
> - }
> -
> data->membase += reg_offset;
>
> return devm_reset_controller_register(dev, &data->rcdev);
> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> new file mode 100644
> index 000000000000..b92769861d2b
> --- /dev/null
> +++ b/drivers/reset/reset-socfpga.c
> @@ -0,0 +1,88 @@
> +// SPDX-License-Identifier: GPL-2.0

I think checkpatch.pl complains about the tab here.

regards
Philipp