Re: [PATCH RE-SEND] clk: tegra: Don't enable already enabled PLLs

From: Peter De Schrijver
Date: Mon Mar 04 2019 - 03:19:03 EST

On Wed, Feb 27, 2019 at 06:15:04PM +0300, Dmitry Osipenko wrote:
> 24.02.2019 18:32, Dmitry Osipenko ÐÐÑÐÑ:
> > Initially Common Clock Framework isn't aware of the clock-enable status,
> > this results in enabling of clocks that were enabled by bootloader. This
> > is not a big deal for a regular clock-gates, but for PLL's it may have
> > some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent
> > clock) may result in extra long period of PLL re-locking.
> >
> > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
> > ---
> Peter (and everyone else), yours r-b and ACK will be appreciated since you kinda already took a look at this patch in the past and were okay with it (IIRC, we had some brief discussion on the #tegra IRC a few months ago), thanks.

Acked-By: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>