Re: [PATCH] MIPS: jz4740: Fix Ingenic SoCs sometimes reporting wrong ISA

From: Paul Cercueil
Date: Tue May 07 2019 - 18:00:05 EST



Le mar. 7 mai 2019 à 23:15, Paul Burton <paul.burton@xxxxxxxx> a écrit :
Hi Paul,

On Tue, May 07, 2019 at 09:41:01PM +0200, Paul Cercueil wrote:
The config0 register in the Xburst always reports a MIPS32r2
ISA, but not all of them support it.

Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
---
arch/mips/jz4740/setup.c | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
index 7e63c54eb8d2..2508c026bdfa 100644
--- a/arch/mips/jz4740/setup.c
+++ b/arch/mips/jz4740/setup.c
@@ -64,6 +64,7 @@ static unsigned long __init get_board_mach_type(const void *fdt)

void __init plat_mem_setup(void)
{
+ struct cpuinfo_mips *c = &current_cpu_data;
int offset;
void *dtb;

@@ -81,6 +82,18 @@ void __init plat_mem_setup(void)
jz4740_detect_mem();

mips_machtype = get_board_mach_type(dtb);
+
+ switch (mips_machtype) {
+ case MACH_INGENIC_JZ4740:
+ /*
+ * The config0 register in the Xburst always reports a MIPS32r2
+ * ISA, but not all of them support it.
+ */
+ c->isa_level &= ~MIPS_CPU_ISA_M32R2;
+ break;
+ default:
+ break;
+ }
}

void __init device_tree_init(void)
--
2.21.0.593.g511ec345e18

Would it work to check the PRID instead? That way we could keep the CPU
probing in cpu-probe.c, for example something like this in
cpu_probe_ingenic():

if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)
c->isa_level &= ~MIPS_CPU_ISA_M32R2;

Smart!

That relies on the D0 PRID always being MIPS32r1 & other PRIDs always
being MIPS32r2 though - do you know whether that's the case? Our
comments in asm/cpu.h mapping the various PRIDs to SoCs suggests this
would be OK to me.

All the SoCs up to the jz4760 (included) have the D0 PRID and are MIPS32r1,
and the first one to use a different PRID is the jz4770 which is also the
first one which is MIPS32r2, so it works perfectly.

Thanks,
Paul