Re: [PATCH 2/2] mtd: spi-nor: intel-spi: add support for Intel Cannon Lake SPI flash

[Mika Westerberg]

Hi Jethro,

On Sat, Aug 31, 2019 at 05:50:34AM +0000, Jethro Beekman wrote:
> (apologies, resending without S/MIME signature)
> 
> Now that SPI flash controllers without a software sequencer are
> supported, it's trivial to add support for CNL and its PCI ID.
> 
> Signed-off-by: Jethro Beekman <jethro@xxxxxxxxxxxx>
> ---
>    drivers/mtd/spi-nor/intel-spi-pci.c     |  5 +++++
>    drivers/mtd/spi-nor/intel-spi.c         | 11 +++++++++++
>    include/linux/platform_data/intel-spi.h |  1 +
>    3 files changed, 17 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/intel-spi-pci.c 
> b/drivers/mtd/spi-nor/intel-spi-pci.c
> index b83c4ab6..195a09d 100644
> --- a/drivers/mtd/spi-nor/intel-spi-pci.c
> +++ b/drivers/mtd/spi-nor/intel-spi-pci.c
> @@ -20,6 +20,10 @@ static const struct intel_spi_boardinfo bxt_info = {
>    	.type = INTEL_SPI_BXT,
>    };
>    +static const struct intel_spi_boardinfo cnl_info = {

Looks like some white space damage. There are couple of similar below as
well.

> +	.type = INTEL_SPI_CNL,
> +};
> +
>    static int intel_spi_pci_probe(struct pci_dev *pdev,
>    			       const struct pci_device_id *id)
>    {
> @@ -67,6 +71,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = {
>    	{ PCI_VDEVICE(INTEL, 0x4b24), (unsigned long)&bxt_info },
>    	{ PCI_VDEVICE(INTEL, 0xa1a4), (unsigned long)&bxt_info },
>    	{ PCI_VDEVICE(INTEL, 0xa224), (unsigned long)&bxt_info },
> +	{ PCI_VDEVICE(INTEL, 0xa324), (unsigned long)&cnl_info },
>    	{ },
>    };
>    MODULE_DEVICE_TABLE(pci, intel_spi_pci_ids);
> diff --git a/drivers/mtd/spi-nor/intel-spi.c 
> b/drivers/mtd/spi-nor/intel-spi.c
> index 195cdca..91b7851 100644
> --- a/drivers/mtd/spi-nor/intel-spi.c
> +++ b/drivers/mtd/spi-nor/intel-spi.c
> @@ -108,6 +108,10 @@
>    #define BXT_FREG_NUM			12
>    #define BXT_PR_NUM			6
>    +#define CNL_PR				0x84

Here.

> +#define CNL_FREG_NUM			6
> +#define CNL_PR_NUM			5
> +
>    #define LVSCC				0xc4
>    #define UVSCC				0xc8
>    #define ERASE_OPCODE_SHIFT		8
> @@ -344,6 +348,13 @@ static int intel_spi_init(struct intel_spi *ispi)
>    		ispi->erase_64k = true;
>    		break;
>    +	case INTEL_SPI_CNL:

And here.

> +		ispi->sregs = NULL;
> +		ispi->pregs = ispi->base + CNL_PR;
> +		ispi->nregions = CNL_FREG_NUM;
> +		ispi->pr_num = CNL_PR_NUM;

Does CNL really have a different number of PR and FR regions than the
previous generations?

> +		break;
> +
>    	default:
>    		return -EINVAL;
>    	}
> diff --git a/include/linux/platform_data/intel-spi.h 
> b/include/linux/platform_data/intel-spi.h
> index ebb4f33..7f53a5c 100644
> --- a/include/linux/platform_data/intel-spi.h
> +++ b/include/linux/platform_data/intel-spi.h
> @@ -13,6 +13,7 @@ enum intel_spi_type {
>    	INTEL_SPI_BYT = 1,
>    	INTEL_SPI_LPT,
>    	INTEL_SPI_BXT,
> +	INTEL_SPI_CNL,
>    };
>     /**
> -- 
> 2.7.4
> 
>