Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
From: Stephen Boyd
Date: Wed Sep 18 2019 - 01:00:55 EST
Quoting Eugen.Hristev@xxxxxxxxxxxxx (2019-09-10 23:39:20)
> From: Eugen Hristev <eugen.hristev@xxxxxxxxxxxxx>
>
> The PLL input range needs to be able to allow 24 Mhz crystal as input
> Update the range accordingly in plla characteristics struct
>
> Signed-off-by: Eugen Hristev <eugen.hristev@xxxxxxxxxxxxx>
> ---
Applied to clk-next