Re: [PATCH] arch/riscv: disable too many harts before pick main boot hart

[Paul Walmsley]

On Fri, 6 Sep 2019, Xiang Wang wrote:

> From 12300865d1103618c9d4c375f7d7fbe601b6618c Mon Sep 17 00:00:00 2001
> From: Xiang Wang <merle@xxxxxxxxxxxxxxxxx>
> Date: Fri, 6 Sep 2019 11:56:09 +0800
> Subject: [PATCH] arch/riscv: disable too many harts before pick main boot hart
> 
> These harts with id greater than or equal to CONFIG_NR_CPUS need to be disabled.
> But pick the main Hart can choose any one. So, before pick the main hart, you
> need to disable the hart with id greater than or equal to CONFIG_NR_CPUS.
> 
> Signed-off-by: Xiang Wang <merle@xxxxxxxxxxxxxxxxx>

Thanks, here's what I'm planning to queue for v5.4-rc1.  Please let me 
know ASAP if you want to change the patch description.


- Paul

From: Xiang Wang <merle@xxxxxxxxxxxxxxxxx>
Date: Fri, 6 Sep 2019 11:56:09 +0800
Subject: [PATCH] arch/riscv: disable excess harts before picking main boot hart

Harts with id greater than or equal to CONFIG_NR_CPUS need to be
disabled.  But the kernel can pick any hart as the main hart.  So,
before picking the main hart, the kernel must disable harts with ids
greater than or equal to CONFIG_NR_CPUS.

Signed-off-by: Xiang Wang <merle@xxxxxxxxxxxxxxxxx>
Reviewed-by: Palmer Dabbelt <palmer@xxxxxxxxxx>
[paul.walmsley@xxxxxxxxxx: updated to apply; cleaned up patch
 description]
Signed-off-by: Paul Walmsley <paul.walmsley@xxxxxxxxxx>
---
 arch/riscv/kernel/head.S | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 15a9189f91ad..72f89b7590dd 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -63,6 +63,11 @@ _start_kernel:
 	li t0, SR_FS
 	csrc CSR_SSTATUS, t0
 
+#ifdef CONFIG_SMP
+	li t0, CONFIG_NR_CPUS
+	bgeu a0, t0, .Lsecondary_park
+#endif
+
 	/* Pick one hart to run the main boot sequence */
 	la a3, hart_lottery
 	li a2, 1
@@ -154,9 +159,6 @@ relocate:
 
 .Lsecondary_start:
 #ifdef CONFIG_SMP
-	li a1, CONFIG_NR_CPUS
-	bgeu a0, a1, .Lsecondary_park
-
 	/* Set trap vector to spin forever to help debug */
 	la a3, .Lsecondary_park
 	csrw CSR_STVEC, a3
-- 
2.23.0