Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180

[Taniya Das]

Hi Rajendra,

Please pick the patch in the series : 
https://patchwork.kernel.org/patch/11150013/

On 9/19/2019 4:38 PM, Rajendra Nayak wrote:
> []..
>
> > +static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
> > +ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
> > +};
>
> this fails to build..
>
> In file included from drivers/clk/qcom/gcc-sc7180.c:17:0:
> drivers/clk/qcom/gcc-sc7180.c:2429:17: error: 
> âgcc_qupv3_wrap0_s0_clk_src_srcâ undeclared here (not in a function)
>  Â DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
>  ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ^
> drivers/clk/qcom/clk-rcg.h:171:12: note: in definition of macro 
> âDEFINE_RCG_DFSâ
>  Â { .rcg = &r##_src, .init = &r##_init }
>  ÂÂÂÂÂÂÂÂÂÂÂ ^
> drivers/clk/qcom/gcc-sc7180.c:2430:17: error: 
> âgcc_qupv3_wrap0_s1_clk_src_srcâ undeclared here (not in a function)
>  Â DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
>  ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ^
> drivers/clk/qcom/clk-rcg.h:171:12: note: in definition of macro 
> âDEFINE_RCG_DFSâ
>  Â { .rcg = &r##_src, .init = &r##_init }
>  ÂÂÂÂÂÂÂÂÂÂÂ ^
> Perhaps you should drop _src here and in the clk_init_data names.
>
> > +
> > +static const struct regmap_config gcc_sc7180_regmap_config = {
> > +ÂÂÂ .reg_bits = 32,
> > +ÂÂÂ .reg_stride = 4,
> > +ÂÂÂ .val_bits = 32,
> > +ÂÂÂ .max_register = 0x18208c,
> > +ÂÂÂ .fast_io = true,
> > +};
> > +
> > +static const struct qcom_cc_desc gcc_sc7180_desc = {
> > +ÂÂÂ .config = &gcc_sc7180_regmap_config,
> > +ÂÂÂ .clk_hws = gcc_sc7180_hws,
> > +ÂÂÂ .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
> > +ÂÂÂ .clks = gcc_sc7180_clocks,
> > +ÂÂÂ .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
> > +ÂÂÂ .resets = gcc_sc7180_resets,
> > +ÂÂÂ .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
> > +ÂÂÂ .gdscs = gcc_sc7180_gdscs,
> > +ÂÂÂ .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
> > +};
> > +
> > +static const struct of_device_id gcc_sc7180_match_table[] = {
> > +ÂÂÂ { .compatible = "qcom,gcc-sc7180" },
> > +ÂÂÂ { }
> > +};
> > +MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
> > +
> > +static int gcc_sc7180_probe(struct platform_device *pdev)
> > +{
> > +ÂÂÂ struct regmap *regmap;
> > +ÂÂÂ int ret;
> > +
> > +ÂÂÂ regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
> > +ÂÂÂ if (IS_ERR(regmap))
> > +ÂÂÂÂÂÂÂ return PTR_ERR(regmap);
> > +
> > +ÂÂÂ /*
> > +ÂÂÂÂ * Disable the GPLL0 active input to MM blocks, NPU
> > +ÂÂÂÂ * and GPU via MISC registers.
> > +ÂÂÂÂ */
> > +ÂÂÂ regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3);
> > +ÂÂÂ regmap_update_bits(regmap, GCC_NPU_MISC, 0x3, 0x3);
> > +ÂÂÂ regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);
> > +
> > +ÂÂÂ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ARRAY_SIZE(gcc_dfs_clocks));
> > +ÂÂÂ if (ret)
> > +ÂÂÂÂÂÂÂ return ret;
> > +
> > +ÂÂÂ return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
> > +}
> > +
> > +static struct platform_driver gcc_sc7180_driver = {
> > +ÂÂÂ .probe = gcc_sc7180_probe,
> > +ÂÂÂ .driver = {
> > +ÂÂÂÂÂÂÂ .name = "gcc-sc7180",
> > +ÂÂÂÂÂÂÂ .of_match_table = gcc_sc7180_match_table,
> > +ÂÂÂ },
> > +};
> > +
> > +static int __init gcc_sc7180_init(void)
> > +{
> > +ÂÂÂ return platform_driver_register(&gcc_sc7180_driver);
> > +}
> > +subsys_initcall(gcc_sc7180_init);
> > +
> > +static void __exit gcc_sc7180_exit(void)
> > +{
> > +ÂÂÂ platform_driver_unregister(&gcc_sc7180_driver);
> > +}
> > +module_exit(gcc_sc7180_exit);
> > +
> > +MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
> > +MODULE_LICENSE("GPL v2");
> > --
> > Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
> > of the Code Aurora Forum, hosted by the Linux Foundation.

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

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