ardb/for-kernelci bisection: boot on ox820-cloudengines-pogoplug-series-3

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Date: Wed Nov 27 2019 - 10:32:45 EST

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ardb/for-kernelci bisection: boot on ox820-cloudengines-pogoplug-series-3

Summary:
Start: 0086acf6c8a3 crypto: remove cipher routines from public crypto API
Details: https://kernelci.org/boot/id/5dde4ea062298c36b5a1b79e
Plain log: https://storage.kernelci.org//ardb/for-kernelci/v5.4-5284-g0086acf6c8a3/arm/oxnas_v6_defconfig/gcc-8/lab-baylibre/boot-ox820-cloudengines-pogoplug-series-3.txt
HTML log: https://storage.kernelci.org//ardb/for-kernelci/v5.4-5284-g0086acf6c8a3/arm/oxnas_v6_defconfig/gcc-8/lab-baylibre/boot-ox820-cloudengines-pogoplug-series-3.html
Result: a639d59db09e ARM/decompressor: avoid CP15 barrier instructions in v7 cache setup code

Checks:
revert: PASS
verify: PASS

Parameters:
Tree: ardb
URL: git://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git
Branch: for-kernelci
Target: ox820-cloudengines-pogoplug-series-3
CPU arch: arm
Lab: lab-baylibre
Compiler: gcc-8
Config: oxnas_v6_defconfig
Test suite: boot

Breaking commit found:

-------------------------------------------------------------------------------
commit a639d59db09e39306fd9958b412170fb8d075e25
Author: Ard Biesheuvel <ardb@xxxxxxxxxx>
Date: Wed Nov 6 09:58:14 2019 +0100

ARM/decompressor: avoid CP15 barrier instructions in v7 cache setup code

Commit e17b1af96b2afc38e684aa2f1033387e2ed10029

"ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache"

added some explicit handling of the CP15BEN bit in the SCTLR system
register, to ensure that CP15 barrier instructions are enabled, even
if we enter the decompressor via the EFI stub.

However, as it turns out, there are other ways in which we may end up
using CP15 barrier instructions without them being enabled. I.e., when
the decompressor startup code skips the cache_on() initially, we end
up calling cache_clean_flush() with the caches and MMU off, in which
case the CP15BEN bit in SCTLR may not be programmed either. And in
fact, cache_on() itself issues CP15 barrier instructions before actually
enabling them by programming the new SCTLR value (and issuing an ISB)

Since all these routines are specific to v7, let's clean this up by
using the ordinary v7 barrier instructions in the v7 specific cache
handling routines, so that we never rely on the CP15 ones. This also
avoids the issue where a barrier is required between programming SCTLR
and using the CP15 barrier instructions, which would result in two
different kinds of barriers being used in the same function.

Signed-off-by: Ard Biesheuvel <ardb@xxxxxxxxxx>

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 93dffed0ac6e..ec14687aea3c 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -656,6 +656,21 @@ params: ldr r0, =0x10000100 @ params_phys for RPC
.align
#endif

+ .macro v7dsb
+ ARM( .inst 0xf57ff04f @ v7+ dsb )
+ THUMB( dsb )
+ .endm
+
+ .macro v7dmb
+ ARM( .inst 0xf57ff05f @ v7+ dmb )
+ THUMB( dmb )
+ .endm
+
+ .macro v7isb
+ ARM( .inst 0xf57ff06f @ v7+ isb )
+ THUMB( isb )
+ .endm
+
/*
* Turn on the cache. We need to setup some page tables so that we
* can have both the I and D caches on.
@@ -827,7 +842,7 @@ __armv7_mmu_cache_on:
movne r6, #CB_BITS | 0x02 @ !XN
blne __setup_mmu
mov r0, #0
- mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
+ v7dsb @ drain write buffer
tst r11, #0xf @ VMSA
mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
#endif
@@ -849,11 +864,11 @@ __armv7_mmu_cache_on:
mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
#endif
- mcr p15, 0, r0, c7, c5, 4 @ ISB
+ v7isb
mcr p15, 0, r0, c1, c0, 0 @ load control register
mrc p15, 0, r0, c1, c0, 0 @ and read it back
mov r0, #0
- mcr p15, 0, r0, c7, c5, 4 @ ISB
+ v7isb
mov pc, r12

__fa526_cache_on:
@@ -1154,8 +1169,8 @@ __armv7_mmu_cache_off:
mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
#endif
mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
- mcr p15, 0, r0, c7, c10, 4 @ DSB
- mcr p15, 0, r0, c7, c5, 4 @ ISB
+ v7dsb
+ v7isb
mov pc, r12

/*
@@ -1218,7 +1233,7 @@ __armv7_mmu_cache_flush:
mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
b iflush
hierarchical:
- mcr p15, 0, r10, c7, c10, 5 @ DMB
+ v7dmb
stmfd sp!, {r0-r7, r9-r11}
mrc p15, 1, r0, c0, c0, 1 @ read clidr
ands r3, r0, #0x7000000 @ extract loc from clidr
@@ -1232,7 +1247,7 @@ loop1:
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
+ v7isb @ isb to sych the new cssr&csidr
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
and r2, r1, #7 @ extract the length of the cache lines
add r2, r2, #4 @ add 4 (line length offset)
@@ -1264,10 +1279,10 @@ finished:
mov r10, #0 @ switch back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
iflush:
- mcr p15, 0, r10, c7, c10, 4 @ DSB
+ v7dsb
mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
- mcr p15, 0, r10, c7, c10, 4 @ DSB
- mcr p15, 0, r10, c7, c5, 4 @ ISB
+ v7dsb
+ v7isb
mov pc, lr

__armv5tej_mmu_cache_flush:
-------------------------------------------------------------------------------

Git bisection log:

-------------------------------------------------------------------------------
git bisect start
# good: [89d57dddd7d319ded00415790a0bb3c954b7e386] Merge tag 'media/v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
git bisect good 89d57dddd7d319ded00415790a0bb3c954b7e386
# bad: [0086acf6c8a3010db4cf2226327c43ae78c18e07] crypto: remove cipher routines from public crypto API
git bisect bad 0086acf6c8a3010db4cf2226327c43ae78c18e07
# bad: [39d72c3eb15d16844565abba94ef2aa9d76526eb] Revert "ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache"
git bisect bad 39d72c3eb15d16844565abba94ef2aa9d76526eb
# bad: [a639d59db09e39306fd9958b412170fb8d075e25] ARM/decompressor: avoid CP15 barrier instructions in v7 cache setup code
git bisect bad a639d59db09e39306fd9958b412170fb8d075e25
# first bad commit: [a639d59db09e39306fd9958b412170fb8d075e25] ARM/decompressor: avoid CP15 barrier instructions in v7 cache setup code
-------------------------------------------------------------------------------

Next message: Charles Keepax: "[PATCH] spi: dw: Correct handling of native chipselect"
Previous message: Pavel Tatashin: "Re: [PATCH v2 3/3] arm64: remove the rest of asm-uaccess.h"
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